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soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent

This commit is contained in:
Florent Kermarrec 2019-05-01 12:58:44 +02:00
parent 9f8f0eb18e
commit 4dccb8a9eb
1 changed files with 4 additions and 2 deletions
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6
litex/soc/interconnect/axi.py
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@ -122,10 +122,12 @@ class AXI2Wishbone(Module):
assert axi.data_width == len(wishbone.dat_r) assert axi.data_width == len(wishbone.dat_r)
assert axi.address_width == len(wishbone.adr) + 2 assert axi.address_width == len(wishbone.adr) + 2
ax_buffer = stream.Buffer(ax_description(axi.address_width, axi.id_width))
ax_burst = stream.Endpoint(ax_description(axi.address_width, axi.id_width)) ax_burst = stream.Endpoint(ax_description(axi.address_width, axi.id_width))
ax_beat = stream.Endpoint(ax_description(axi.address_width, axi.id_width)) ax_beat = stream.Endpoint(ax_description(axi.address_width, axi.id_width))
ax_burst2beat = AXIBurst2Beat(ax_burst, ax_beat) self.comb += ax_burst.connect(ax_buffer.sink)
self.submodules += ax_burst2beat ax_burst2beat = AXIBurst2Beat(ax_buffer.source, ax_beat)
self.submodules += ax_buffer, ax_burst2beat
_data = Signal(axi.data_width) _data = Signal(axi.data_width)
_addr = Signal(axi.address_width) _addr = Signal(axi.address_width)