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soc: Replace remaining add_wb_master call by self.bus.add_master.

This commit is contained in:
Florent Kermarrec 2022-01-28 18:41:52 +01:00
parent 162231fb8f
commit 4de54387d3
2 changed files with 3 additions and 3 deletions
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4
litex/soc/integration/soc.py
View File

@ -1530,7 +1530,7 @@ class LiteXSoC(SoC):
self.check_if_exists(name)
etherbone = LiteEthEtherbone(ethcore.udp, udp_port, buffer_depth=buffer_depth, cd=name)
setattr(self.submodules, name, etherbone)
self.add_wb_master(etherbone.wishbone.bus)
self.bus.add_master(master=etherbone.wishbone.bus)
# Timing constraints
if with_timing_constraints:
@ -1753,8 +1753,8 @@ class LiteXSoC(SoC):
# MMAP.
self.check_if_exists(f"{name}_mmap")
mmap = LitePCIeWishboneMaster(self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_wb_master(mmap.wishbone)
setattr(self.submodules, f"{name}_mmap", mmap)
self.bus.add_master(master=mmap.wishbone)
# MSI.
if with_msi:

2
litex/tools/litex_sim.py
View File

@ -233,7 +233,7 @@ class SimSoC(SoCCore):
self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8)
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
self.bus.add_master(master=self.etherbone.wishbone.bus)
# Ethernet ---------------------------------------------------------------------------------
elif with_ethernet: