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https://github.com/enjoy-digital/litex.git
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simplify bist
This commit is contained in:
Florent Kermarrec
parent
1c03f72252
commit
4deda89dcb
5 changed files with 113 additions and 151 deletions
145
lib/sata/bist.py
145
lib/sata/bist.py
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@ -2,23 +2,25 @@ from lib.sata.common import *
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from lib.sata.link.scrambler import Scrambler
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from migen.bank.description import *
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class SATABISTUnit(Module):
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class SATABIST(Module):
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def __init__(self, sata_con):
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self.write = Signal()
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self.read = Signal()
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self.sector = Signal(48)
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self.count = Signal(16)
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self.loops = Signal(8)
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self.done = Signal()
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self.errors = Signal(32)
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###
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sink = sata_con.source
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source = sata_con.sink
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self.start = Signal()
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self.write_only = Signal()
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self.read_only = Signal()
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self.sector = Signal(48)
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self.count = Signal(16)
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self.done = Signal()
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self.ctrl_errors = Signal(32)
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self.data_errors = Signal(32)
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self.counter = counter = Counter(bits_sign=32)
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self.ctrl_error_counter = Counter(self.ctrl_errors, bits_sign=32)
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self.data_error_counter = Counter(self.data_errors, bits_sign=32)
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self.loops_counter = loops_counter = Counter(bits_sign=8)
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self.error_counter = Counter(self.errors, bits_sign=32)
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self.scrambler = scrambler = InsertReset(Scrambler())
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self.comb += [
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@ -30,39 +32,39 @@ class SATABISTUnit(Module):
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fsm.act("IDLE",
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self.done.eq(1),
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counter.reset.eq(1),
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If(self.start,
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self.ctrl_error_counter.reset.eq(1),
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self.data_error_counter.reset.eq(1),
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If(self.read_only,
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NextState("SEND_READ_CMD")
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).Else(
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loops_counter.reset.eq(1),
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If(self.write,
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self.error_counter.reset.eq(1),
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NextState("SEND_WRITE_CMD_AND_DATA")
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)
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).Elif(self.read,
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self.error_counter.reset.eq(1),
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NextState("SEND_READ_CMD")
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)
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)
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fsm.act("SEND_WRITE_CMD_AND_DATA",
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source.stb.eq(1),
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source.sop.eq((counter.value == 0)),
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source.eop.eq((counter.value == (logical_sector_size//4*self.count)-1)),
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source.sop.eq(counter.value == 0),
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source.eop.eq(counter.value == (logical_sector_size//4*self.count)-1),
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source.write.eq(1),
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source.sector.eq(self.sector),
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source.count.eq(self.count),
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source.data.eq(scrambler.value),
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counter.ce.eq(source.ack),
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If(source.stb & source.eop & source.ack,
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If(source.stb & source.ack,
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counter.ce.eq(1),
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If(source.eop,
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NextState("WAIT_WRITE_ACK")
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)
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)
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)
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fsm.act("WAIT_WRITE_ACK",
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sink.ack.eq(1),
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If(sink.stb,
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If(~sink.write | ~sink.success | sink.failed,
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self.ctrl_error_counter.ce.eq(1)
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),
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If(self.write_only,
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loops_counter.ce.eq(1),
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If(loops_counter.value == (self.loops-1),
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NextState("IDLE")
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).Else(
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NextState("SEND_READ_CMD")
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counter.reset.eq(1),
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NextState("SEND_WRITE_CMD_AND_DATA")
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)
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)
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)
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@ -80,9 +82,6 @@ class SATABISTUnit(Module):
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)
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fsm.act("WAIT_READ_ACK",
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If(sink.stb & sink.read,
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If(~sink.read | ~sink.success | sink.failed,
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self.ctrl_error_counter.ce.eq(1)
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),
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NextState("RECEIVE_READ_DATA")
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)
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)
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@ -91,11 +90,16 @@ class SATABISTUnit(Module):
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If(sink.stb,
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counter.ce.eq(1),
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If(sink.data != scrambler.value,
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self.data_error_counter.ce.eq(1)
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self.error_counter.ce.eq(1)
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),
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If(sink.eop,
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If(sink.last,
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loops_counter.ce.eq(1),
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If(loops_counter.value == (self.loops-1),
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NextState("IDLE")
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).Else(
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NextState("SEND_READ_CMD")
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)
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).Else(
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NextState("WAIT_READ_ACK")
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)
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@ -103,71 +107,24 @@ class SATABISTUnit(Module):
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)
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)
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class SATABIST(Module, AutoCSR):
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def __init__(self, sata_con):
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self._start = CSR()
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self._start_sector = CSRStorage(48)
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class SATABISTControl(Module, AutoCSR):
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def __init__(self, sata_bist):
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self._write = CSR()
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self._read = CSR()
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self._sector = CSRStorage(48)
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self._count = CSRStorage(16)
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self._write_only = CSRStorage()
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self._read_only = CSRStorage()
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self._loops = CSRStorage(8)
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self._stop = CSRStorage()
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self._sector = CSRStatus(48)
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self._done = CSRStatus()
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self._errors = CSRStatus(32)
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start = self._start.r & self._start.re
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start_sector = self._start_sector.storage
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count = self._count.storage
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stop = self._stop.storage
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compute = Signal()
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write_only = self._write_only.storage
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read_only = self._read_only.storage
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sector = self._sector.status
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errors = self._errors.status
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###
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self.unit = SATABISTUnit(sata_con)
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self.comb += [
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self.unit.write_only.eq(write_only),
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self.unit.read_only.eq(read_only),
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self.unit.sector.eq(sector),
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self.unit.count.eq(count)
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]
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self.fsm = fsm = FSM(reset_state="IDLE")
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# FSM
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fsm.act("IDLE",
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If(start,
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NextState("START")
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)
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)
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fsm.act("START",
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self.unit.start.eq(1),
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NextState("WAIT_DONE")
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)
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fsm.act("WAIT_DONE",
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If(self.unit.done,
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NextState("COMPUTE")
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).Elif(stop,
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NextState("IDLE")
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)
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)
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fsm.act("COMPUTE",
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compute.eq(1),
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NextState("START")
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)
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self.sync += [
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If(start,
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errors.eq(0),
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sector.eq(start_sector)
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).Elif(compute,
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errors.eq(errors + self.unit.data_errors),
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sector.eq(sector + count)
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)
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sata_bist.write.eq(self._write.r & self._write.re),
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sata_bist.read.eq(self._read.r & self._read.re),
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sata_bist.sector.eq(self._sector.storage),
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sata_bist.count.eq(self._count.storage),
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sata_bist.loops.eq(self._loops.storage),
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self._done.status.eq(sata_bist.done),
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self._errors.status.eq(sata_bist.errors)
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]
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@ -1,6 +1,6 @@
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from lib.sata.common import *
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from lib.sata import SATACON
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from lib.sata.bist import SATABISTUnit
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from lib.sata.bist import SATABIST
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from lib.sata.test.hdd import *
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from lib.sata.test.common import *
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@ -12,21 +12,28 @@ class TB(Module):
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transport_debug=False, transport_loopback=False,
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hdd_debug=True)
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self.con = SATACON(self.hdd.phy)
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self.bist = SATABISTUnit(self.con)
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self.bist = SATABIST(self.con)
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def gen_simulation(self, selfp):
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hdd = self.hdd
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hdd.malloc(0, 64)
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selfp.bist.sector = 0
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selfp.bist.count = 17
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selfp.bist.loops = 1
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while True:
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selfp.bist.start = 1
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selfp.bist.write = 1
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yield
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selfp.bist.start = 0
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selfp.bist.write = 0
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yield
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while selfp.bist.done == 0:
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yield
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print("ctrl_errors: {} / data_errors {}".format(selfp.bist.ctrl_errors, selfp.bist.data_errors))
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selfp.bist.read = 1
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yield
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selfp.bist.read = 0
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yield
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while selfp.bist.done == 0:
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yield
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print("errors {}".format(selfp.bist.errors))
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selfp.bist.sector += 1
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selfp.bist.count = max((selfp.bist.count + 1)%8, 1)
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@ -13,7 +13,7 @@ from misoclib import identifier
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from lib.sata.common import *
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from lib.sata.phy import SATAPHY
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from lib.sata import SATACON
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from lib.sata.bist import SATABIST
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from lib.sata.bist import SATABIST, SATABISTControl
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from migen.genlib.cdc import *
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@ -159,7 +159,7 @@ class DebugLeds(Module):
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class TestDesign(UART2WB, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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"sata_bist": 10,
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"sata_bist_ctrl": 10,
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"mila": 11
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}
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csr_map.update(UART2WB.csr_map)
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@ -172,6 +172,8 @@ class TestDesign(UART2WB, AutoCSR):
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self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, speed="SATA2")
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self.sata_con = SATACON(self.sata_phy)
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self.sata_bist = SATABIST(self.sata_con)
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self.sata_bist_ctrl = SATABISTControl(self.sata_bist)
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self.leds = DebugLeds(platform, self.sata_phy)
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84
test/bist.py
84
test/bist.py
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@ -7,47 +7,24 @@ logical_sector_size = 512
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class SATABISTDriver:
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def __init__(self, regs):
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self.regs = regs
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self.last_sector = 0
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self.last_time = time.time()
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self.last_errors = 0
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self.mode = "rw"
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def set_mode(self, mode):
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self.mode = mode
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self.regs.sata_bist_write_only.write(0)
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self.regs.sata_bist_read_only.write(0)
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if mode == "wr":
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self.regs.sata_bist_write_only.write(1)
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if mode == "rd":
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self.regs.sata_bist_read_only.write(1)
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def run(self, sector, count, loops, mode):
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self.regs.sata_bist_ctrl_sector.write(sector)
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self.regs.sata_bist_ctrl_count.write(count)
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self.regs.sata_bist_ctrl_loops.write(loops)
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if mode == "write":
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self.regs.sata_bist_ctrl_write.write(1)
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elif mode == "read":
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self.regs.sata_bist_ctrl_read.write(1)
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while (self.regs.sata_bist_ctrl_done.read() == 0):
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pass
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return self.regs.sata_bist_ctrl_errors.read()
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def start(self, sector, count, mode):
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self.set_mode(mode)
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self.regs.sata_bist_start_sector.write(sector)
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self.regs.sata_bist_count.write(count)
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self.regs.sata_bist_stop.write(0)
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self.regs.sata_bist_start.write(1)
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def stop(self):
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self.regs.sata_bist_stop.write(1)
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def show_status(self):
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errors = self.regs.sata_bist_errors.read() - self.last_errors
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self.last_errors += errors
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sector = self.regs.sata_bist_sector.read()
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n = sector - self.last_sector
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self.last_sector = sector
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t = self.last_time - time.time()
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self.last_time = time.time()
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if self.mode in ["wr", "rd"]:
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speed_mult = 1
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else:
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speed_mult = 2
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print("%4.2f MB/sec errors=%d sector=%d" %(n*logical_sector_size*speed_mult/(1024*1024), errors, sector))
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def write(self, sector, count, loops):
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self.run(sector, count, loops, "write")
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def read(self, sector, count, loops):
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return self.run(sector, count, loops, "read")
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def _get_args():
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parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
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@ -55,8 +32,8 @@ def _get_args():
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SATA BIST utility.
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""")
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parser.add_argument("-s", "--sector", default=0, help="BIST start sector")
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parser.add_argument("-c", "--count", default=4, help="BIST count (number of sectors per transaction)")
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parser.add_argument("-m", "--mode", default="rw", help="BIST mode (rw, wr, rd")
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parser.add_argument("-c", "--count", default=16384, help="BIST count (number of sectors per transaction)")
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parser.add_argument("-l", "--loops", default=4, help="BIST loops (number of loop for each transaction")
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return parser.parse_args()
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@ -65,13 +42,32 @@ if __name__ == "__main__":
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wb.open()
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###
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bist = SATABISTDriver(wb.regs)
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sector = int(args.sector)
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count = int(args.count)
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loops = int(args.loops)
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try:
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bist.start(int(args.sector), int(args.count), args.mode)
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write_time = 0
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read_time = 0
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while True:
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bist.show_status()
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time.sleep(1)
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# Write
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start = time.time()
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bist.write(sector, count, loops)
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end = time.time()
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write_time = end-start
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write_speed = loops*count*logical_sector_size/(1024*1024)/write_time
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# Read
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start = time.time()
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read_errors = bist.read(sector, count, loops)
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end = time.time()
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read_time = end-start
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read_speed = loops*count*logical_sector_size/(1024*1024)/read_time
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sector += count
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print("sector=%d write_speed=%4.2fMB/sec read_speed=%4.2fMB/sec errors=%d" %(sector, write_speed, read_speed, read_errors))
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except KeyboardInterrupt:
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pass
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bist.stop()
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###
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wb.close()
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@ -27,9 +27,9 @@ mila.prog_sum("term")
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# Trigger / wait / receive
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mila.trigger(offset=32, length=1024)
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bist.start(0, 4, "rw")
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bist.write(0, 16, 1)
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bist.read(0, 16, 1)
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mila.wait_done()
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bist.stop()
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mila.read()
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mila.export("dump.vcd")
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