soc/software: only keep 32-bit CSR alignment support.

64-bit support was added for 64-bit CPU because of limitation of the hardware
on CSR accesses. Now that the Wihhbone2CSR bus handles wishbone.sel, this is no
longer required.

litex/soc/integration/soc.py

@@ -437,7 +437,7 @@ class SoCLocHandler(Module):
 class SoCCSRHandler(SoCLocHandler):
     supported_data_width    = [8, 32]
     supported_address_width = [14+i for i in range(4)]
-    supported_alignment     = [32, 64]
+    supported_alignment     = [32]
     supported_paging        = [0x800*2**i for i in range(4)]
 
     # Creation -------------------------------------------------------------------------------------
@@ -505,21 +505,6 @@ class SoCCSRHandler(SoCLocHandler):
 
         self.logger.info("CSR Handler {}.".format(colorer("created", color="green")))
 
-    # Update CSR Alignment ----------------------------------------------------------------------------
-    def update_alignment(self, alignment):
-        # Check Alignment
-        if alignment not in self.supported_alignment:
-            self.logger.error("Unsupported {}: {} supporteds: {:s}".format(
-                colorer("Alignment", color="red"),
-                colorer(alignment),
-                colorer(", ".join(str(x) for x in self.supported_alignment))))
-            raise
-        self.logger.info("Alignment {} from {}-bit to {}-bit.".format(
-            colorer("updated", color="cyan"),
-            colorer(self.alignment),
-            colorer(alignment)))
-        self.alignment = alignment
-
     # Add Master -----------------------------------------------------------------------------------
     def add_master(self, name=None, master=None):
         if name is None:
@@ -652,7 +637,6 @@ class SoC(Module):
 
         csr_data_width       = 32,
         csr_address_width    = 14,
-        csr_alignment        = 32,
         csr_paging           = 0x800,
         csr_reserved_csrs    = {},
 
@@ -692,7 +676,7 @@ class SoC(Module):
         self.submodules.csr = SoCCSRHandler(
             data_width    = csr_data_width,
             address_width = csr_address_width,
-            alignment     = csr_alignment,
+            alignment     = 32,
             paging        = csr_paging,
             reserved_csrs = csr_reserved_csrs,
         )
@@ -791,7 +775,6 @@ class SoC(Module):
         self.mem_map.update(self.cpu.mem_map) # FIXME
         # Add Bus Masters/CSR/IRQs
         if not isinstance(self.cpu, cpu.CPUNone):
-            self.csr.update_alignment(self.cpu.data_width)
             if reset_address is None:
                 reset_address = self.mem_map["rom"]
             self.cpu.set_reset_address(reset_address)

litex/soc/integration/soc_core.py

@@ -82,7 +82,6 @@ class SoCCore(LiteXSoC):
         integrated_main_ram_init = [],
         # CSR parameters
         csr_data_width           = 8,
-        csr_alignment            = 32,
         csr_address_width        = 14,
         csr_paging               = 0x800,
         # Identifier parameters
@@ -111,7 +110,6 @@ class SoCCore(LiteXSoC):
 
             csr_data_width       = csr_data_width,
             csr_address_width    = csr_address_width,
-            csr_alignment        = csr_alignment,
             csr_paging           = csr_paging,
             csr_reserved_csrs    = self.csr_map,
 

litex/soc/software/bios/main.c

@@ -107,9 +107,8 @@ int main(int i, char **c)
 		CONFIG_BUS_STANDARD,
 		CONFIG_BUS_DATA_WIDTH,
 		(1 << (CONFIG_BUS_ADDRESS_WIDTH - 30)));
-	printf("\e[1mCSR\e[0m:       %d-bit data - %d-bit aligned\n",
+	printf("\e[1mCSR\e[0m:       %d-bit data\n",
-		CONFIG_CSR_DATA_WIDTH,
+		CONFIG_CSR_DATA_WIDTH);
-		CONFIG_CSR_ALIGNMENT);
 	printf("\e[1mROM\e[0m:       %dKiB\n", ROM_SIZE/1024);
 	printf("\e[1mSRAM\e[0m:      %dKiB\n", SRAM_SIZE/1024);
 #ifdef CONFIG_L2_SIZE

litex/soc/software/include/hw/common.h

@@ -20,30 +20,13 @@
  * (base) address. */
 
 #include <generated/soc.h>
-#if !defined(CONFIG_CSR_ALIGNMENT) || !defined(CONFIG_CSR_DATA_WIDTH)
+#if !defined(CONFIG_CSR_DATA_WIDTH)
-#error csr alignment and data-width MUST be set before including this file!
+#error CSR_DATA_WIDTH MUST be set before including this file!
 #endif
 
-#if CONFIG_CSR_DATA_WIDTH > CONFIG_CSR_ALIGNMENT
+/* CSR subregisters (a.k.a. "simple CSRs") are embedded inside uint32_t
-#error invalid CONFIG_CSR_DATA_WIDTH (must not exceed CONFIG_CSR_ALIGNMENT)!
-#endif
-
-/* FIXME: preprocessor can't evaluate 'sizeof()' operator, is there a better
- * way to implement the following assertion?
- * #if sizeof(unsigned long) != CONFIG_CSR_ALIGNMENT/8
- * #error invalid CONFIG_CSR_ALIGNMENT (must match native CPU word size)!
- * #endif
- */
-
-/* CSR subregisters (a.k.a. "simple CSRs") are embedded inside native CPU-word
  * aligned locations: */
-#if CONFIG_CSR_ALIGNMENT == 32
 #define MMPTR(a) (*((volatile uint32_t *)(a)))
-#elif CONFIG_CSR_ALIGNMENT == 64
-#define MMPTR(a) (*((volatile uint64_t *)(a)))
-#else
-#error Unsupported CSR alignment
-#endif
 
 static inline void csr_write_simple(unsigned long v, unsigned long a)
 {
@@ -61,7 +44,7 @@ static inline unsigned long csr_read_simple(unsigned long a)
 
 /* CSR data width (subreg. width) in bytes, for direct comparson to sizeof() */
 #define CSR_DW_BYTES     (CONFIG_CSR_DATA_WIDTH/8)
-#define CSR_OFFSET_BYTES (CONFIG_CSR_ALIGNMENT/8)
+#define CSR_OFFSET_BYTES 4
 
 #ifndef __ASSEMBLER__