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targets/ulx3s,versa_ecp5: prjtrellis toolchain renamed to trellis

This commit is contained in:
Florent Kermarrec 2018-11-12 10:47:33 +01:00
parent cb86728ad1
commit 4ff241b981
2 changed files with 2 additions and 2 deletions
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2
litex/boards/targets/ulx3s.py
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@ -56,7 +56,7 @@ class _CRG(Module):
class BaseSoC(SoCSDRAM):
def __init__(self, **kwargs):
platform = ulx3s.Platform(toolchain="prjtrellis")
platform = ulx3s.Platform(toolchain="trellis")
sys_clk_freq = int(25e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
l2_size=32,

2
litex/boards/targets/versa_ecp5.py
View File

@ -58,7 +58,7 @@ class _CRG(Module):
class BaseSoC(SoCSDRAM):
def __init__(self, **kwargs):
platform = versa_ecp5.Platform(toolchain="prjtrellis")
platform = versa_ecp5.Platform(toolchain="trellis")
platform.add_extension(versa_ecp5._ecp5_soc_hat_io)
sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,