Corelogic conversion example
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from migen.fhdl import structure as f
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from migen.fhdl import verilog
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from migen.corelogic import roundrobin, divider
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r = roundrobin.Inst(5)
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d = divider.Inst(16)
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frag = r.GetFragment() + d.GetFragment()
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o = verilog.Convert(frag, {r.request, r.grant, d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
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print(o)
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from migen.fhdl import structure as f
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from migen.fhdl import verilog
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from functools import partial
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class Divider:
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def __init__(self, w):
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self.w = w
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d = partial(f.Declare, self)
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d("start_i")
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d("dividend_i", f.BV(w))
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d("divisor_i", f.BV(w))
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d("ready_o")
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d("quotient_o", f.BV(w))
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d("remainder_o", f.BV(w))
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d("_qr", f.BV(2*w))
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d("_counter", f.BV(f.BitsFor(w)))
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d("_divisor_r", f.BV(w))
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d("_diff", f.BV(w+1))
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def GetFragment(self):
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a = f.Assign
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comb = [
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a(self.quotient_o, self._qr[:self.w]),
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a(self.remainder_o, self._qr[self.w:]),
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a(self.ready_o, self._counter == f.Constant(0, self._counter.bv)),
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a(self._diff, self.remainder_o - self._divisor_r)
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]
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sync = [
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f.If(self.start_i == 1, [
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a(self._counter, self.w),
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a(self._qr, self.dividend_i),
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a(self._divisor_r, self.divisor_i)
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], [
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f.If(self.ready_o == 0, [
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f.If(self._diff[self.w] == 1,
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[a(self._qr, f.Cat(0, self._qr[:2*self.w-1]))],
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[a(self._qr, f.Cat(1, self._qr[:self.w-1], self._diff[:self.w]))]),
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a(self._counter, self._counter - f.Constant(1, self._counter.bv)),
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])
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])
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]
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return f.Fragment(comb, sync)
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d = Divider(32)
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frag = d.GetFragment()
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o = verilog.Convert(frag, {d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
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print(o)
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from migen.fhdl import structure as f
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from migen.fhdl import structure as f
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from functools import partial
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class Inst:
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class Inst:
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def __init__(self, w):
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def __init__(self, w):
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@ -40,4 +41,4 @@ class Inst:
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])
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])
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])
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])
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]
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]
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return f.Fragment(comb, sync)
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return f.Fragment(comb, sync)
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