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soc/add_spi_flash: Reduce LiteSPIPHY default divisor to max(2, self.sys_clk_freq/clk_freq). 

One small FPGAs running the BIOS from SPI Flash, the default divisor of 9 was slowing down too
much BIOS boot time (It was OK on reboot after liblitespi auto-calibration). Reduce the default
divisor to avoid this.
This commit is contained in:
Florent Kermarrec 2021-07-29 17:16:38 +02:00
parent 14d60661b9
commit 505c8b85d6
1 changed files with 1 additions and 1 deletions
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2
litex/soc/integration/soc.py
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@ -1514,7 +1514,7 @@ class LiteXSoC(SoC):
self.check_if_exists(name + "_phy")
self.check_if_exists(name + "_mmap")
spiflash_pads = self.platform.request(name if mode == "1x" else name + mode)
spiflash_phy = LiteSPIPHY(spiflash_pads, module)
spiflash_phy = LiteSPIPHY(spiflash_pads, module, default_divisor=max(int(self.sys_clk_freq/clk_freq), 2))
spiflash_mmap = LiteSPI(spiflash_phy, clk_freq=clk_freq, mmap_endianness=self.cpu.endianness, **kwargs)
setattr(self.submodules, name + "_phy", spiflash_phy)
setattr(self.submodules, name + "_mmap", spiflash_mmap)