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cores/video: Regroup VGA/DVI Phy in VideoGenericPHY and support variations (positive/negative hsync/vsync, etc...)

This commit is contained in:
Florent Kermarrec 2021-06-09 08:25:23 +02:00
parent 25ead1ad69
commit 5061a368da
1 changed files with 25 additions and 39 deletions
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50
litex/soc/cores/video.py
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@ -656,36 +656,9 @@ class VideoFrameBuffer(Module, AutoCSR):
class Open(Signal): pass class Open(Signal): pass
# VGA (Generic). # Generic (Very Generic PHY supporting VGA/DVI and variations).
class VideoVGAPHY(Module): class VideoGenericPHY(Module):
def __init__(self, pads, clock_domain="sys"):
self.sink = sink = stream.Endpoint(video_data_layout)
# # #
# Always ack Sink, no backpressure.
self.comb += sink.ready.eq(1)
# Drive VGA Clk (Optional).
if hasattr(pads, "clk"):
self.comb += pads.clk.eq(ClockSignal(clock_domain))
# Drive VGA Conrols.
self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain))
# Drive VGA Datas.
cbits = len(pads.r)
cshift = (8 - cbits)
for i in range(cbits):
self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
# DVI (Generic).
class VideoDVIPHY(Module):
def __init__(self, pads, clock_domain="sys", with_clk_ddr_output=True): def __init__(self, pads, clock_domain="sys", with_clk_ddr_output=True):
self.sink = sink = stream.Endpoint(video_data_layout) self.sink = sink = stream.Endpoint(video_data_layout)
@ -694,19 +667,24 @@ class VideoDVIPHY(Module):
# Always ack Sink, no backpressure. # Always ack Sink, no backpressure.
self.comb += sink.ready.eq(1) self.comb += sink.ready.eq(1)
# Drive DVI Clk. # Drive Clk.
if hasattr(pads, "clk"):
if with_clk_ddr_output: if with_clk_ddr_output:
self.specials += DDROutput(i1=1, i2=0, o=pads.clk, clk=ClockSignal(clock_domain)) self.specials += DDROutput(i1=1, i2=0, o=pads.clk, clk=ClockSignal(clock_domain))
else: else:
self.comb += pads.clk.eq(ClockSignal(clock_domain)) self.comb += pads.clk.eq(ClockSignal(clock_domain))
# Drive DVI Controls. # Drive Controls.
if hasattr(pads, "de"): if hasattr(pads, "de"):
self.specials += SDROutput(i=sink.de, o=pads.de, clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.de, o=pads.de, clk=ClockSignal(clock_domain))
if hasattr(pads, "hsync_n") and hasattr(pads, "vsync_n"):
self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain))
else:
self.specials += SDROutput(i=sink.hsync, o=pads.hsync, clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.hsync, o=pads.hsync, clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=sink.vsync, o=pads.vsync, clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.vsync, o=pads.vsync, clk=ClockSignal(clock_domain))
# Drive DVI Datas. # Drive Datas.
cbits = len(pads.r) cbits = len(pads.r)
cshift = (8 - cbits) cshift = (8 - cbits)
for i in range(cbits): for i in range(cbits):
@ -714,6 +692,14 @@ class VideoDVIPHY(Module):
self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
# VGA (Generic).
class VideoVGAPHY(VideoGenericPHY): pass
# DVI (Generic).
class VideoDVIPHY(VideoGenericPHY): pass
# HDMI (Generic). # HDMI (Generic).
class VideoHDMI10to1Serializer(Module): class VideoHDMI10to1Serializer(Module):