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soc/ethernet: enable full_memory_we by default for Quartus toolchain

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Piotr Wegrzyn 2024-12-13 22:33:39 +01:00
parent f63d4a8334
commit 50e5df4ffb
1 changed files with 4 additions and 1 deletions
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5
litex/soc/integration/soc.py
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@ -1841,7 +1841,7 @@ class LiteXSoC(SoC):
data_width = 8,
nrxslots = 2, rxslots_read_only = True,
ntxslots = 2, txslots_write_only = False,
full_memory_we = False,
full_memory_we = None,
with_timestamp = False,
with_timing_constraints = True,
local_ip = None,
@ -1850,6 +1850,7 @@ class LiteXSoC(SoC):
# Imports
from liteeth.mac import LiteEthMAC
from liteeth.phy.model import LiteEthPHYModel
from litex.build.altera.quartus import AlteraQuartusToolchain
# MAC.
assert data_width in [8, 32, 64]
@ -1857,6 +1858,8 @@ class LiteXSoC(SoC):
self.check_if_exists(name)
if with_timestamp:
self.timer0.add_uptime()
if full_memory_we is None:
full_memory_we = isinstance(self.platform.toolchain, AlteraQuartusToolchain)
ethmac = LiteEthMAC(
phy = phy,
dw = {8: 32, 32: 32, 64: 64}[data_width],