integration/soc_core: Move L2/SDRAM arguments soc_core_args.
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@ -55,15 +55,6 @@ class SoCSDRAM(SoCCore):
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def soc_sdram_args(parser):
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def soc_sdram_args(parser):
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soc_core_args(parser)
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soc_core_args(parser)
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# L2 Cache
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parser.add_argument("--l2-size", default=8192, type=auto_int,
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help="L2 cache size (default=8192)")
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parser.add_argument("--min-l2-data-width", default=128, type=auto_int,
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help="Minimum L2 cache datawidth (default=128)")
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# SDRAM
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parser.add_argument("--max-sdram-size", default=0x40000000, type=auto_int,
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help="Maximum SDRAM size mapped to the SoC (default=1GB))")
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def soc_sdram_argdict(args):
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def soc_sdram_argdict(args):
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r = soc_core_argdict(args)
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r = soc_core_argdict(args)
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@ -299,6 +299,12 @@ def soc_core_args(parser):
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parser.add_argument("--no-timer", action="store_true", help="Disable Timer (default=False).")
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parser.add_argument("--no-timer", action="store_true", help="Disable Timer (default=False).")
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parser.add_argument("--timer-uptime", action="store_true", help="Add an uptime capability to Timer (default=False).")
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parser.add_argument("--timer-uptime", action="store_true", help="Add an uptime capability to Timer (default=False).")
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# L2 Cache
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parser.add_argument("--l2-size", default=8192, type=auto_int, help="L2 cache size (default=8192).")
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parser.add_argument("--min-l2-data-width", default=128, type=auto_int, help="Minimum L2 cache datawidth (default=128).")
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# SDRAM
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parser.add_argument("--max-sdram-size", default=0x40000000, type=auto_int, help="Maximum SDRAM size mapped to the SoC (default=1GB))")
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def soc_core_argdict(args):
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def soc_core_argdict(args):
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r = dict()
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r = dict()
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