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integration/soc_core: Move L2/SDRAM arguments soc_core_args.

This commit is contained in:
Florent Kermarrec 2021-03-24 13:39:21 +01:00
parent ad63f8edc8
commit 50ed5e262d
2 changed files with 6 additions and 9 deletions
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9
litex/compat/soc_sdram.py
View File

@ -55,15 +55,6 @@ class SoCSDRAM(SoCCore):
def soc_sdram_args(parser):
soc_core_args(parser)
# L2 Cache
parser.add_argument("--l2-size", default=8192, type=auto_int,
help="L2 cache size (default=8192)")
parser.add_argument("--min-l2-data-width", default=128, type=auto_int,
help="Minimum L2 cache datawidth (default=128)")
# SDRAM
parser.add_argument("--max-sdram-size", default=0x40000000, type=auto_int,
help="Maximum SDRAM size mapped to the SoC (default=1GB))")
def soc_sdram_argdict(args):
r = soc_core_argdict(args)

6
litex/soc/integration/soc_core.py
View File

@ -299,6 +299,12 @@ def soc_core_args(parser):
parser.add_argument("--no-timer", action="store_true", help="Disable Timer (default=False).")
parser.add_argument("--timer-uptime", action="store_true", help="Add an uptime capability to Timer (default=False).")
# L2 Cache
parser.add_argument("--l2-size", default=8192, type=auto_int, help="L2 cache size (default=8192).")
parser.add_argument("--min-l2-data-width", default=128, type=auto_int, help="Minimum L2 cache datawidth (default=128).")
# SDRAM
parser.add_argument("--max-sdram-size", default=0x40000000, type=auto_int, help="Maximum SDRAM size mapped to the SoC (default=1GB))")
def soc_core_argdict(args):
r = dict()