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soc/interconnect/axi: generate wishbone.sel for reads.

This commit is contained in:
Florent Kermarrec 2020-06-01 10:58:45 +02:00
parent 4f82a36afd
commit 511832a911
1 changed files with 1 additions and 0 deletions
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litex/soc/interconnect/axi.py
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@ -365,6 +365,7 @@ class AXILite2Wishbone(Module):
wishbone.stb.eq(1), wishbone.stb.eq(1),
wishbone.cyc.eq(1), wishbone.cyc.eq(1),
wishbone.adr.eq(_r_addr[wishbone_adr_shift:]), wishbone.adr.eq(_r_addr[wishbone_adr_shift:]),
wishbone.sel.eq(2**len(wishbone.sel) - 1),
If(wishbone.ack, If(wishbone.ack,
axi_lite.ar.ready.eq(1), axi_lite.ar.ready.eq(1),
NextValue(_data, wishbone.dat_r), NextValue(_data, wishbone.dat_r),