soc/interconnect/axi: generate wishbone.sel for reads.

2020-06-01 10:58:45 +02:00 · 2020-06-01 10:58:45 +02:00 · 511832a911
parent 4f82a36afd
commit 511832a911
1 changed files with 1 additions and 0 deletions
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@ -365,6 +365,7 @@ class AXILite2Wishbone(Module):
            wishbone.stb.eq(1),
            wishbone.cyc.eq(1),
            wishbone.adr.eq(_r_addr[wishbone_adr_shift:]),
+            wishbone.sel.eq(2**len(wishbone.sel) - 1),
            If(wishbone.ack,
                axi_lite.ar.ready.eq(1),
                NextValue(_data, wishbone.dat_r),