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build/io/InferedSDRTristate: pass clock domain to SDROutput/SDRInput.

This commit is contained in:
Florent Kermarrec 2020-07-07 12:11:47 +02:00
parent 23dfefb9be
commit 51f2e6ce64
1 changed files with 2 additions and 2 deletions
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4
litex/build/io.py
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@ -81,8 +81,8 @@ class InferedSDRTristate(Module):
_o = Signal() _o = Signal()
_oe = Signal() _oe = Signal()
_i = Signal() _i = Signal()
self.specials += SDROutput(o, _o) self.specials += SDROutput(o, _o, clk)
self.specials += SDRInput(_i, i) self.specials += SDRInput(_i, i, clk)
self.submodules += InferedSDRIO(oe, _oe, clk, clk_domain) self.submodules += InferedSDRIO(oe, _oe, clk, clk_domain)
self.specials += Tristate(io, _o, _oe, _i) self.specials += Tristate(io, _o, _oe, _i)