bus/wishbone/SRAM: support init and read_only
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7ada0159fd
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5208baada8
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@ -184,12 +184,17 @@ class Target(Module):
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bus.ack = 0
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class SRAM(Module):
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def __init__(self, mem_or_size, bus=None):
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def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
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if isinstance(mem_or_size, Memory):
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assert(mem_or_size.width <= 32)
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mem = mem_or_size
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else:
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mem = Memory(32, mem_or_size//4)
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mem = Memory(32, mem_or_size//4, init=init)
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if read_only is None:
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if hasattr(mem, "bus_read_only"):
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read_only = mem.bus_read_only
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else:
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read_only = False
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if bus is None:
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bus = Interface()
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self.bus = bus
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@ -198,16 +203,18 @@ class SRAM(Module):
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# memory
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self.specials += mem
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port = mem.get_port(write_capable=True, we_granularity=8)
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port = mem.get_port(write_capable=not read_only, we_granularity=8)
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# generate write enable signal
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if not read_only:
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self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
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for i in range(4)]
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# address and data
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self.comb += [
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port.adr.eq(self.bus.adr[:len(port.adr)]),
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port.dat_w.eq(self.bus.dat_w),
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self.bus.dat_r.eq(port.dat_r)
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]
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if not read_only:
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self.comb += port.dat_w.eq(self.bus.dat_w),
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# generate ack
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self.sync += [
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self.bus.ack.eq(0),
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