bus/wishbone: add SRAM
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@ -193,3 +193,33 @@ class Target(PureSimulable):
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bus.ack = 1
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else:
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bus.ack = 0
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class SRAM:
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def __init__(self, mem_or_size, bus=Interface()):
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if isinstance(mem_or_size, Memory):
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assert(mem_or_size.width == 32)
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self.mem = mem_or_size
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else:
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self.mem = Memory(32, mem_or_size//4)
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self.bus = bus
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def get_fragment(self):
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# memory
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port = self.mem.get_port(write_capable=True, we_granularity=8)
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# generate write enable signal
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comb = [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
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for i in range(4)]
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# address and data
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comb += [
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port.adr.eq(self.bus.adr[:len(port.adr)]),
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port.dat_w.eq(self.bus.dat_w),
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self.bus.dat_r.eq(port.dat_r)
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]
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# generate ack
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sync = [
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self.bus.ack.eq(0),
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If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
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self.bus.ack.eq(1)
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)
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]
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return Fragment(comb, sync, memories=[self.mem])
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