pytholite: fix bit width of selection signal

2012-11-30 17:07:32 +01:00 · 2012-11-30 17:07:32 +01:00 · adb1565d7a
parent cfb23c442f
commit adb1565d7a
1 changed files with 1 additions and 1 deletions
--- a/migen/pytholite/reg.py
+++ b/migen/pytholite/reg.py
@ -40,7 +40,7 @@ class ImplRegister:
 	def finalize(self):
 		if self.finalized:
 			raise FinalizeError
-		self.sel = Signal(max=len(self.source_encoding)+2, name="pl_regsel_"+self.name)
+		self.sel = Signal(max=len(self.source_encoding)+1, name="pl_regsel_"+self.name)
 		self.finalized = True
 	
 	def get_fragment(self):