altera/jtag: Minor cosmetic cleanups, avoid some duplications.
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@ -12,6 +12,15 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import *
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# Common JTAG --------------------------------------------------------------------------------------
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altera_reserved_jtag_pads = [
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"altera_reserved_tms",
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"altera_reserved_tck",
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"altera_reserved_tdi",
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"altera_reserved_tdo",
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]
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# Common AsyncResetSynchronizer --------------------------------------------------------------------
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class AlteraAsyncResetSynchronizerImpl(Module):
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@ -53,17 +53,10 @@ class AlteraPlatform(GenericPlatform):
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self.toolchain.add_false_path_constraint(self, from_, to)
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def add_reserved_jtag_decls(self):
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self.add_extension([
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("altera_reserved_tms", 0, Pins("altera_reserved_tms")),
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("altera_reserved_tck", 0, Pins("altera_reserved_tck")),
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("altera_reserved_tdi", 0, Pins("altera_reserved_tdi")),
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("altera_reserved_tdo", 0, Pins("altera_reserved_tdo")),
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])
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self.add_extension([*[(pad, 0, Pins(pad)) for pad in common.altera_reserved_jtag_pads]])
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def get_reserved_jtag_pads(self):
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return {
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"altera_reserved_tms": self.request("altera_reserved_tms"),
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"altera_reserved_tck": self.request("altera_reserved_tck"),
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"altera_reserved_tdi": self.request("altera_reserved_tdi"),
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"altera_reserved_tdo": self.request("altera_reserved_tdo"),
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}
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r = {}
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for pad in common.altera_reserved_jtag_pads:
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r[pad] = self.request(pad)
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return r
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@ -12,7 +12,6 @@
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from migen import *
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from migen.genlib.cdc import AsyncResetSynchronizer, MultiReg
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from litex.gen.fhdl.fsm import CorrectedOngoingResetFSM
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from litex.soc.interconnect import stream
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# JTAG TAP FSM -------------------------------------------------------------------------------------
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@ -160,12 +159,12 @@ class JTAGTAPFSM(Module):
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class AlteraJTAG(Module):
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def __init__(self, primitive, reserved_pads):
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# Common with Xilinx
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self.reset = reset = Signal() # provided by our own TAP FSM
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self.capture = capture = Signal() # provided by our own TAP FSM
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# Common with Xilinx.
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self.reset = reset = Signal() # Provided by our own TAP FSM.
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self.capture = capture = Signal() # Provided by our own TAP FSM.
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self.shift = shift = Signal()
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self.update = update = Signal()
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# Unique to Altera
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# Unique to Altera.
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self.runtest = runtest = Signal()
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self.drck = drck = Signal()
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self.sel = sel = Signal()
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@ -175,49 +174,49 @@ class AlteraJTAG(Module):
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self.tdi = tdi = Signal()
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self.tdo = tdo = Signal()
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# magic reserved signals that have to be routed to the top module
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# Magic reserved signals that have to be routed to the top module.
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self.altera_reserved_tck = rtck = Signal()
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self.altera_reserved_tms = rtms = Signal()
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self.altera_reserved_tdi = rtdi = Signal()
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self.altera_reserved_tdo = rtdo = Signal()
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# inputs
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# Inputs.
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self.tdouser = tdouser = Signal()
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# outputs
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# Outputs.
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self.tmsutap = tmsutap = Signal()
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self.tckutap = tckutap = Signal()
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self.tdiutap = tdiutap = Signal()
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# # #
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# create falling-edge JTAG clock domain for TAP FSM
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# Create falling-edge JTAG clock domain for TAP FSM.
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self.clock_domains.cd_jtag_inv = cd_jtag_inv = ClockDomain("jtag_inv")
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self.comb += ClockSignal("jtag_inv").eq(~ClockSignal("jtag"))
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self.comb += ResetSignal("jtag_inv").eq(ResetSignal("jtag"))
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# connect the TAP state signals that LiteX expects but the HW IP doesn't provide
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# Connect the TAP state signals that LiteX expects but the HW IP doesn't provide.
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self.submodules.tap_fsm = ClockDomainsRenamer("jtag")(JTAGTAPFSM(tms))
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self.sync.jtag_inv += reset.eq(self.tap_fsm.TEST_LOGIC_RESET)
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self.sync.jtag_inv += capture.eq(self.tap_fsm.CAPTURE_DR)
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self.specials += Instance(primitive,
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# HW TAP FSM states
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o_shiftuser = shift,
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o_updateuser = update,
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o_runidleuser = runtest,
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o_clkdruser = drck,
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o_usr1user = sel,
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# JTAG TAP IO
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i_tdouser = tdouser,
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o_tmsutap = tmsutap,
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o_tckutap = tckutap,
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o_tdiutap = tdiutap,
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# reserved pins
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i_tms = rtms,
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i_tck = rtck,
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i_tdi = rtdi,
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o_tdo = rtdo,
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# HW TAP FSM states.
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o_shiftuser = shift,
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o_updateuser = update,
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o_runidleuser = runtest,
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o_clkdruser = drck,
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o_usr1user = sel,
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# JTAG TAP IO.
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i_tdouser = tdouser,
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o_tmsutap = tmsutap,
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o_tckutap = tckutap,
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o_tdiutap = tdiutap,
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# Reserved pins.
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i_tms = rtms,
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i_tck = rtck,
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i_tdi = rtdi,
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o_tdo = rtdo,
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)
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# connect magical reserved signals to top level pads
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@ -228,7 +227,7 @@ class AlteraJTAG(Module):
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reserved_pads["altera_reserved_tdo"].eq(rtdo),
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]
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# connect TAP IO
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# Connect TAP IO.
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self.comb += [
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tck.eq(tckutap),
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tms.eq(tmsutap),
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