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FIXME: flip polarity of reverse for downconverter case

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Not sure what is driving this, but, empirically the bytes
are being swapped on the read path.

Unfortunately the stride converter only has the ability to
swap both at the same time, not one or the other.

Could be possible that maybe the solution is to write the data
into the memory in reverse order of what is expected? not sure.
This commit is contained in:
bunnie 2022-11-17 03:31:07 +08:00
parent 912c6e0138
commit 5397623a7a
1 changed files with 1 additions and 1 deletions
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2
litex/soc/interconnect/stream.py
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@ -453,7 +453,7 @@ class _DownConverter(Module):
# Data path # Data path
cases = {} cases = {}
for i in range(ratio): for i in range(ratio):
n = ratio-i-1 if reverse else i n = ratio-i-1 if not reverse else i # FIXME: flipped polarity for AXI stream case. Need to figure out how to make more generic?
cases[i] = source.data.eq(sink.data[n*nbits_to:(n+1)*nbits_to]) cases[i] = source.data.eq(sink.data[n*nbits_to:(n+1)*nbits_to])
self.comb += Case(mux, cases).makedefault() self.comb += Case(mux, cases).makedefault()