FIXME: flip polarity of reverse for downconverter case

Not sure what is driving this, but, empirically the bytes
are being swapped on the read path.

Unfortunately the stride converter only has the ability to
swap both at the same time, not one or the other.

Could be possible that maybe the solution is to write the data
into the memory in reverse order of what is expected? not sure.

litex/soc/interconnect/stream.py

@@ -453,7 +453,7 @@ class _DownConverter(Module):
         # Data path
         cases = {}
         for i in range(ratio):
-            n = ratio-i-1 if reverse else i
+            n = ratio-i-1 if not reverse else i # FIXME: flipped polarity for AXI stream case. Need to figure out how to make more generic?
             cases[i] = source.data.eq(sink.data[n*nbits_to:(n+1)*nbits_to])
         self.comb += Case(mux, cases).makedefault()