wire up missing register bits.

Not sure how they went missing...but just noticed them.
2020-07-19 03:00:25 +08:00 · 2020-07-19 03:00:25 +08:00 · 53a567daef
parent 63c19ff45f
commit 53a567daef
1 changed files with 2 additions and 0 deletions
--- a/litex/soc/cores/i2s.py
+++ b/litex/soc/cores/i2s.py
@ -283,10 +283,12 @@ class S7I2S(Module, AutoCSR, AutoDoc):
                o_WRERR       = rx_wrerr,
            )
            self.comb += [  # Wire up the status signals and interrupts
+                self.rx_stat.fields.overflow.eq(rx_wrerr),
                self.rx_stat.fields.underflow.eq(rx_rderr),
                self.rx_stat.fields.dataready.eq(rx_almostfull),
                self.rx_stat.fields.wrcount.eq(rx_wrcount),
                self.rx_stat.fields.rdcount.eq(rx_rdcount),
+                self.rx_stat.fields.empty.eq(rx_empty),
                self.ev.rx_ready.trigger.eq(rx_almostfull),
                self.ev.rx_error.trigger.eq(rx_wrerr | rx_rderr),
            ]