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wire up missing register bits.

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Not sure how they went missing...but just noticed them.
This commit is contained in:
bunnie 2020-07-19 03:00:25 +08:00
parent 63c19ff45f
commit 53a567daef
1 changed files with 2 additions and 0 deletions
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2
litex/soc/cores/i2s.py
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@ -283,10 +283,12 @@ class S7I2S(Module, AutoCSR, AutoDoc):
o_WRERR = rx_wrerr, o_WRERR = rx_wrerr,
) )
self.comb += [ # Wire up the status signals and interrupts self.comb += [ # Wire up the status signals and interrupts
self.rx_stat.fields.overflow.eq(rx_wrerr),
self.rx_stat.fields.underflow.eq(rx_rderr), self.rx_stat.fields.underflow.eq(rx_rderr),
self.rx_stat.fields.dataready.eq(rx_almostfull), self.rx_stat.fields.dataready.eq(rx_almostfull),
self.rx_stat.fields.wrcount.eq(rx_wrcount), self.rx_stat.fields.wrcount.eq(rx_wrcount),
self.rx_stat.fields.rdcount.eq(rx_rdcount), self.rx_stat.fields.rdcount.eq(rx_rdcount),
self.rx_stat.fields.empty.eq(rx_empty),
self.ev.rx_ready.trigger.eq(rx_almostfull), self.ev.rx_ready.trigger.eq(rx_almostfull),
self.ev.rx_error.trigger.eq(rx_wrerr | rx_rderr), self.ev.rx_error.trigger.eq(rx_wrerr | rx_rderr),
] ]