cpu/blackparrot: first cleanup pass
This commit is contained in:
Florent Kermarrec
parent
f3829cf081
commit
53ee9a5e05
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@ -1,4 +1,3 @@
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# litex/soc/cores/cpu/blackparrot/core.py
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# BlackParrot Chip core support for the LiteX SoC.
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#
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# Authors: Sadullah Canakci & Cansu Demirkiran <{scanakci,cansu}@bu.edu>
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@ -39,25 +38,20 @@ from litex.soc.cores.cpu import CPU
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CPU_VARIANTS = {
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"standard": "freechips.rocketchip.system.LitexConfig",
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# "linux": "freechips.rocketchip.system.LitexLinuxConfig",
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# "full": "freechips.rocketchip.system.LitexFullConfig",
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}
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GCC_FLAGS = {
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"standard": "-march=rv64ia -mabi=lp64 -O0 ",
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# "linux": "-march=rv64imac -mabi=lp64 ",
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# "full": "-march=rv64imafdc -mabi=lp64 ",
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}
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class BlackParrotRV64(Module):
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class BlackParrotRV64(CPU):
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name = "blackparrot"
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data_width = 64
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endianness = "little"
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gcc_triple = ("riscv64-unknown-elf")
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gcc_triple = ("riscv64-unknown-elf", "riscv64-linux")
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linker_output_format = "elf64-littleriscv"
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# io_regions = {0x10000000: 0x70000000} # origin, length
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io_regions = {0x30000000: 0x20000000} # origin, length
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@property
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def mem_map(self):
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return {
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@ -77,71 +71,53 @@ class BlackParrotRV64(Module):
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def __init__(self, platform, variant="standard"):
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assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
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print("SC: Check how to get cpu_reset_addr properly!!!!!!!!")
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#assert cpu_reset_addr == 0x10000000, "cpu_reset_addr hardcoded in Chisel elaboration!"
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self.platform = platform
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self.variant = variant
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self.reset = Signal()
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self.interrupt = Signal(4)#TODO: how interrupts work?
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# print(self.interrupt)
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# old self.wbone = wbn = wishbone.Interface(data_width=64, adr_width=40)
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self.wbone = wbn = wishbone.Interface(data_width=64, adr_width=37)
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self.platform = platform
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self.variant = variant
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self.reset = Signal()
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self.interrupt = Signal(4)
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self.idbus = idbus = wishbone.Interface(data_width=64, adr_width=37)
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self.buses = [idbus]
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self.interrupts = {}#TODO: Idk why this is necessary. Without this, soc_core.py raises error with no object attirubute "interrupts"
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self.buses = [wbn]
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# # #
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# connect BP adaptor to Wishbone
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self.cpu_params = dict(
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# clock, reset
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i_clk_i = ClockSignal(),
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i_reset_i = ResetSignal() | self.reset,
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i_clk_i = ClockSignal(),
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i_reset_i = ResetSignal() | self.reset,
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# irq
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i_interrupts = self.interrupt,
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i_wbm_dat_i = wbn.dat_r,
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o_wbm_dat_o = wbn.dat_w,
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i_wbm_ack_i = wbn.ack,
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# i_wbm_err_i = wbn.err,
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# i_wbm_rty_i = wbn.try,
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o_wbm_adr_o = wbn.adr,
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o_wbm_stb_o = wbn.stb,
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o_wbm_cyc_o = wbn.cyc,
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o_wbm_sel_o = wbn.sel,
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o_wbm_we_o = wbn.we,
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o_wbm_cti_o = wbn.cti,
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o_wbm_bte_o = wbn.bte,
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# wishbone
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i_wbm_dat_i = idbus.dat_r,
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o_wbm_dat_o = idbus.dat_w,
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i_wbm_ack_i = idbus.ack,
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i_wbm_err_i = 0,
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i_wbm_rty_i = 0,
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o_wbm_adr_o = idbus.adr,
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o_wbm_stb_o = idbus.stb,
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o_wbm_cyc_o = idbus.cyc,
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o_wbm_sel_o = idbus.sel,
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o_wbm_we_o = idbus.we,
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o_wbm_cti_o = idbus.cti,
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o_wbm_bte_o = idbus.bte,
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)
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# self.submodules += mem_a2w, mmio_a2w #need to change most probably!
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# add verilog sources
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# add verilog sources
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self.add_sources(platform, variant)
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def set_reset_address(self, reset_address):#note sure if reset address needs to be changed for BB
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def set_reset_address(self, reset_address):
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assert not hasattr(self, "reset_address")
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self.reset_address = reset_address
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print(hex(reset_address))
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#assert reset_address == 0x10000000, "cpu_reset_addr hardcoded in during elaboration!"
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assert reset_address == 0x00000000, "cpu_reset_addr hardcoded to 0x00000000!"
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@staticmethod
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def add_sources(platform, variant="standard"):
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#Read from a file and use add_source function
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# vdir = os.path.join(
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#os.path.abspath(os.path.dirname(__file__)),"pre-alpha-release", "verilog",variant)
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# incdir = os.path.join(
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#os.path.abspath(os.path.dirname(__file__)),"pre-alpha-release", "verilog",variant)
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print("Adding the sources")
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#vdir = os.path.join(
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#os.path.abspath(os.path.dirname(__file__)),"verilog")
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#platform.add_source_dir(vdir)
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filename= os.path.join(os.path.abspath(os.path.dirname(__file__)),"flist_litex.verilator")
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print(filename)
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# platform.add_source('/home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_fpga/ExampleBlackParrotSystem.v')
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filename = os.path.join(os.path.abspath(os.path.dirname(__file__)), "flist_litex.verilator")
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with open(filename) as openfileobject:
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for line in openfileobject:
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temp = line
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# print(line)
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if (temp[0] == '/' and temp[1] == '/'):
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continue
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elif ("+incdir+" in temp) :
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@ -164,9 +140,6 @@ class BlackParrotRV64(Module):
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elif (temp[0] == '/'):
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assert("No support for absolute path for now")
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.specials += Instance("ExampleBlackParrotSystem", **self.cpu_params)
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