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integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs.

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This commit is contained in:
Florent Kermarrec 2020-02-20 16:16:07 +01:00
parent 3a6f97fff3
commit f3829cf081
1 changed files with 2 additions and 1 deletions
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3
litex/soc/integration/soc.py
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@ -1001,4 +1001,5 @@ class LiteXSoC(SoC):
self.add_config("L2_SIZE", l2_cache_size)
# Wishbone Slave <--> LiteDRAM bridge --------------------------------------------------
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port)
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port,
base_address = self.bus.regions["main_ram"].origin)