cpu/blackparrot: first cleanup pass
This commit is contained in:
Florent Kermarrec
parent
f3829cf081
commit
53ee9a5e05
|
|
@ -1,4 +1,3 @@
|
|||
# litex/soc/cores/cpu/blackparrot/core.py
|
||||
# BlackParrot Chip core support for the LiteX SoC.
|
||||
#
|
||||
# Authors: Sadullah Canakci & Cansu Demirkiran <{scanakci,cansu}@bu.edu>
|
||||
|
|
@ -39,23 +38,18 @@ from litex.soc.cores.cpu import CPU
|
|||
|
||||
CPU_VARIANTS = {
|
||||
"standard": "freechips.rocketchip.system.LitexConfig",
|
||||
# "linux": "freechips.rocketchip.system.LitexLinuxConfig",
|
||||
# "full": "freechips.rocketchip.system.LitexFullConfig",
|
||||
}
|
||||
|
||||
GCC_FLAGS = {
|
||||
"standard": "-march=rv64ia -mabi=lp64 -O0 ",
|
||||
# "linux": "-march=rv64imac -mabi=lp64 ",
|
||||
# "full": "-march=rv64imafdc -mabi=lp64 ",
|
||||
}
|
||||
|
||||
class BlackParrotRV64(Module):
|
||||
class BlackParrotRV64(CPU):
|
||||
name = "blackparrot"
|
||||
data_width = 64
|
||||
endianness = "little"
|
||||
gcc_triple = ("riscv64-unknown-elf")
|
||||
gcc_triple = ("riscv64-unknown-elf", "riscv64-linux")
|
||||
linker_output_format = "elf64-littleriscv"
|
||||
# io_regions = {0x10000000: 0x70000000} # origin, length
|
||||
io_regions = {0x30000000: 0x20000000} # origin, length
|
||||
|
||||
@property
|
||||
|
|
@ -77,71 +71,53 @@ class BlackParrotRV64(Module):
|
|||
|
||||
def __init__(self, platform, variant="standard"):
|
||||
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
|
||||
print("SC: Check how to get cpu_reset_addr properly!!!!!!!!")
|
||||
#assert cpu_reset_addr == 0x10000000, "cpu_reset_addr hardcoded in Chisel elaboration!"
|
||||
|
||||
self.platform = platform
|
||||
self.variant = variant
|
||||
self.reset = Signal()
|
||||
self.interrupt = Signal(4)#TODO: how interrupts work?
|
||||
# print(self.interrupt)
|
||||
# old self.wbone = wbn = wishbone.Interface(data_width=64, adr_width=40)
|
||||
self.wbone = wbn = wishbone.Interface(data_width=64, adr_width=37)
|
||||
self.platform = platform
|
||||
self.variant = variant
|
||||
self.reset = Signal()
|
||||
self.interrupt = Signal(4)
|
||||
self.idbus = idbus = wishbone.Interface(data_width=64, adr_width=37)
|
||||
self.buses = [idbus]
|
||||
|
||||
self.interrupts = {}#TODO: Idk why this is necessary. Without this, soc_core.py raises error with no object attirubute "interrupts"
|
||||
|
||||
self.buses = [wbn]
|
||||
# # #
|
||||
# connect BP adaptor to Wishbone
|
||||
|
||||
self.cpu_params = dict(
|
||||
# clock, reset
|
||||
i_clk_i = ClockSignal(),
|
||||
i_reset_i = ResetSignal() | self.reset,
|
||||
i_clk_i = ClockSignal(),
|
||||
i_reset_i = ResetSignal() | self.reset,
|
||||
|
||||
# irq
|
||||
i_interrupts = self.interrupt,
|
||||
i_wbm_dat_i = wbn.dat_r,
|
||||
o_wbm_dat_o = wbn.dat_w,
|
||||
i_wbm_ack_i = wbn.ack,
|
||||
# i_wbm_err_i = wbn.err,
|
||||
# i_wbm_rty_i = wbn.try,
|
||||
o_wbm_adr_o = wbn.adr,
|
||||
o_wbm_stb_o = wbn.stb,
|
||||
o_wbm_cyc_o = wbn.cyc,
|
||||
o_wbm_sel_o = wbn.sel,
|
||||
o_wbm_we_o = wbn.we,
|
||||
o_wbm_cti_o = wbn.cti,
|
||||
o_wbm_bte_o = wbn.bte,
|
||||
|
||||
# wishbone
|
||||
i_wbm_dat_i = idbus.dat_r,
|
||||
o_wbm_dat_o = idbus.dat_w,
|
||||
i_wbm_ack_i = idbus.ack,
|
||||
i_wbm_err_i = 0,
|
||||
i_wbm_rty_i = 0,
|
||||
o_wbm_adr_o = idbus.adr,
|
||||
o_wbm_stb_o = idbus.stb,
|
||||
o_wbm_cyc_o = idbus.cyc,
|
||||
o_wbm_sel_o = idbus.sel,
|
||||
o_wbm_we_o = idbus.we,
|
||||
o_wbm_cti_o = idbus.cti,
|
||||
o_wbm_bte_o = idbus.bte,
|
||||
)
|
||||
|
||||
# self.submodules += mem_a2w, mmio_a2w #need to change most probably!
|
||||
# add verilog sources
|
||||
# add verilog sources
|
||||
self.add_sources(platform, variant)
|
||||
|
||||
def set_reset_address(self, reset_address):#note sure if reset address needs to be changed for BB
|
||||
def set_reset_address(self, reset_address):
|
||||
assert not hasattr(self, "reset_address")
|
||||
self.reset_address = reset_address
|
||||
print(hex(reset_address))
|
||||
#assert reset_address == 0x10000000, "cpu_reset_addr hardcoded in during elaboration!"
|
||||
|
||||
assert reset_address == 0x00000000, "cpu_reset_addr hardcoded to 0x00000000!"
|
||||
|
||||
@staticmethod
|
||||
def add_sources(platform, variant="standard"):
|
||||
#Read from a file and use add_source function
|
||||
# vdir = os.path.join(
|
||||
#os.path.abspath(os.path.dirname(__file__)),"pre-alpha-release", "verilog",variant)
|
||||
# incdir = os.path.join(
|
||||
#os.path.abspath(os.path.dirname(__file__)),"pre-alpha-release", "verilog",variant)
|
||||
print("Adding the sources")
|
||||
#vdir = os.path.join(
|
||||
#os.path.abspath(os.path.dirname(__file__)),"verilog")
|
||||
#platform.add_source_dir(vdir)
|
||||
filename= os.path.join(os.path.abspath(os.path.dirname(__file__)),"flist_litex.verilator")
|
||||
print(filename)
|
||||
# platform.add_source('/home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_fpga/ExampleBlackParrotSystem.v')
|
||||
filename = os.path.join(os.path.abspath(os.path.dirname(__file__)), "flist_litex.verilator")
|
||||
with open(filename) as openfileobject:
|
||||
for line in openfileobject:
|
||||
temp = line
|
||||
# print(line)
|
||||
if (temp[0] == '/' and temp[1] == '/'):
|
||||
continue
|
||||
elif ("+incdir+" in temp) :
|
||||
|
|
@ -164,9 +140,6 @@ class BlackParrotRV64(Module):
|
|||
elif (temp[0] == '/'):
|
||||
assert("No support for absolute path for now")
|
||||
|
||||
|
||||
|
||||
|
||||
def do_finalize(self):
|
||||
assert hasattr(self, "reset_address")
|
||||
self.specials += Instance("ExampleBlackParrotSystem", **self.cpu_params)
|
||||
|
|
|
|||
Loading…
Reference in New Issue