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gensdrphy: fix memtype and change phase shift in comments.

This commit is contained in:
Florent Kermarrec 2014-05-16 11:46:33 +02:00 committed by Sebastien Bourdeauducq
parent 6298624f98
commit 54339a6d5b
1 changed files with 2 additions and 2 deletions
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4
misoclib/sdramphy/gensdrphy.py
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@ -7,7 +7,7 @@
# The PHY needs 2 Clock domains: # The PHY needs 2 Clock domains:
# - sys_clk : The System Clock domain # - sys_clk : The System Clock domain
# - sys_clk_ps : The System Clock domain with its phase shifted # - sys_clk_ps : The System Clock domain with its phase shifted
# (-0.75ns on C4@100MHz) # (-3ns on C4@100MHz)
# #
# Assert dfi_wrdata_en and present the data # Assert dfi_wrdata_en and present the data
# on dfi_wrdata_mask/dfi_wrdata in the same # on dfi_wrdata_mask/dfi_wrdata in the same
@ -35,7 +35,7 @@ class GENSDRPHY(Module):
d = flen(pads.dq) d = flen(pads.dq)
self.phy_settings = lasmicon.PhySettings( self.phy_settings = lasmicon.PhySettings(
memtype=memtype, memtype="SDR",
dfi_d=d, dfi_d=d,
nphases=1, nphases=1,
rdphase=0, rdphase=0,