use new submodules/specials/clock_domains automatic collection

miscope/mila.py

@@ -67,15 +67,15 @@ class MiLa(Module, AutoCSR):
 				sink.dat.eq(dat)
 			]
 
-		self.submodules.trigger = trigger = Trigger(self.width, self.ports)
-		self.submodules.recorder = recorder = Recorder(self.width, self.depth)
+		self.trigger = trigger = Trigger(self.width, self.ports)
+		self.recorder = recorder = Recorder(self.width, self.depth)
 		self.comb += [
 			sink.connect(trigger.sink),
 			trigger.source.connect(recorder.trig_sink)
 		]
 
 		if self.with_rle:
-			self.submodules.rle = rle = RunLengthEncoder(self.width)
+			self.rle = rle = RunLengthEncoder(self.width)
 			self.comb += [
 				sink.connect(rle.sink),
 				rle.source.connect(recorder.dat_sink)

miscope/trigger.py

@@ -124,9 +124,9 @@ class Trigger(Module, AutoCSR):
 		self.width = width
 		self.ports = ports
 
-		self.submodules.sum = Sum(len(ports))
+		self.sum = Sum(len(ports))
 		for i, port in enumerate(ports):
-			setattr(self.submodules, "port"+str(i), port)
+			setattr(self, "port"+str(i), port)
 
 		self.sink   = Record(dat_layout(width))
 		self.source = self.sum.source

miscope/uart2wishbone.py

@@ -14,8 +14,8 @@ class UART(Module, AutoCSR):
 
 		###
 
-		self.submodules.rx = UARTRX(pads, tuning_word)
-		self.submodules.tx = UARTTX(pads, tuning_word)
+		self.rx = UARTRX(pads, tuning_word)
+		self.tx = UARTTX(pads, tuning_word)
 
 class Counter(Module):
 	def __init__(self, width):
@@ -75,12 +75,12 @@ class UART2Wishbone(Module, AutoCSR):
 
 	###
 		if share_uart:
-			self.submodules.uart_mux = UARTMux(pads)
-			self.submodules.uart = UART(self.uart_mux.bridge_pads, clk_freq, baud)
+			self.uart_mux = UARTMux(pads)
+			self.uart = UART(self.uart_mux.bridge_pads, clk_freq, baud)
 			self.shared_pads = self.uart_mux.shared_pads
 			self.comb += self.uart_mux.sel.eq(self._sel.storage)
 		else:
-			self.submodules.uart = UART(pads, clk_freq, baud)
+			self.uart = UART(pads, clk_freq, baud)
 
 		uart = self.uart
 

sim/tb_recorder_csr.py

@@ -40,7 +40,7 @@ def csr_configure(bus, regs):
 
 	# Offset
 	regs.recorder_offset.write(0)
-	
+
 	# Trigger
 	regs.recorder_trigger.write(1)
 
@@ -58,7 +58,7 @@ def csr_transactions(bus, regs):
 
 	for t in range(100):
 		yield None
-	
+
 	global triggered
 	triggered = True
 
@@ -81,10 +81,10 @@ class TB(Module):
 		self.csr_base = 0
 
 		# Recorder
-		self.submodules.recorder = Recorder(32, 1024)
-	
+		self.recorder = Recorder(32, 1024)
+
 		# Csr
-		self.submodules.csrbankarray = csrgen.BankArray(self, 
+		self.csrbankarray = csrgen.BankArray(self,
 			lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
 
 		# Csr Master
@@ -93,16 +93,16 @@ class TB(Module):
 
 		bus = Csr2Trans()
 		regs = build_map(addrmap, bus.read_csr, bus.write_csr)
-		self.submodules.master = csr.Initiator(csr_transactions(bus, regs))
+		self.master = csr.Initiator(csr_transactions(bus, regs))
 
-		self.submodules.csrcon = csr.Interconnect(self.master.bus,	self.csrbankarray.get_buses())
+		self.csrcon = csr.Interconnect(self.master.bus,	self.csrbankarray.get_buses())
 
 	# Recorder Data
 	def recorder_data(self, selfp):
 		selfp.recorder.dat_sink.stb = 1
 		if not hasattr(self, "cnt"):
 			self.cnt = 0
-		self.cnt += 1	
+		self.cnt += 1
 
 		selfp.recorder.dat_sink.dat =  self.cnt
 

sim/tb_rle.py

@@ -24,9 +24,9 @@ rle_test_seq = iter(
 
 class TB(Module):
 	def __init__(self):
-		
+
 		# Rle
-		self.submodules.rle = storage.RunLengthEncoder(16, 32)
+		self.rle = storage.RunLengthEncoder(16, 32)
 
 	def do_simulation(self, selfp):
 		selfp.rle._r_enable.storage = 1

sim/tb_trigger_csr.py

@@ -22,7 +22,7 @@ class Csr2Trans():
 
 	def read_csr(self, adr):
 		self.t.append(TRead(adr//4))
-	
+
 def csr_prog_mila(bus, regs):
 	regs.trigger_port0_mask.write(0xFFFFFFFF)
 	regs.trigger_port0_trig.write(0xDEADBEEF)
@@ -60,27 +60,27 @@ class TB(Module):
 	}
 	def __init__(self, addrmap=None):
 		self.csr_base = 0
-			
+
 		# Trigger
 		term0 = Term(32)
 		term1 = Term(32)
 		term2 = Term(32)
 		term3 = Term(32)
-		self.submodules.trigger = Trigger(32, [term0, term1, term2, term3])
-	
+		self.trigger = Trigger(32, [term0, term1, term2, term3])
+
 		# Csr
-		self.submodules.csrbankarray = csrgen.BankArray(self, 
+		self.csrbankarray = csrgen.BankArray(self,
 			lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
-		
+
 		# Csr Master
 		csr_header = get_csr_csv(self.csr_base, self.csrbankarray)
 		write_to_file("csr.csv", csr_header)
-		
+
 		bus = Csr2Trans()
 		regs = build_map(addrmap, bus.read_csr, bus.write_csr)
-		self.submodules.master = csr.Initiator(csr_transactions(bus, regs))
-		
-		self.submodules.csrcon = csr.Interconnect(self.master.bus,	self.csrbankarray.get_buses())
+		self.master = csr.Initiator(csr_transactions(bus, regs))
+
+		self.csrcon = csr.Interconnect(self.master.bus,	self.csrbankarray.get_buses())
 
 		self.terms = [term0, term1, term2, term3]