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use new submodules/specials/clock_domains automatic collection

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This commit is contained in:
Florent Kermarrec 2015-01-12 12:40:47 +01:00
parent 834e9b99be
commit 54597f1bfc
6 changed files with 30 additions and 30 deletions
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6
miscope/mila.py
View file

@ -67,15 +67,15 @@ class MiLa(Module, AutoCSR):
sink.dat.eq(dat) sink.dat.eq(dat)
] ]
self.submodules.trigger = trigger = Trigger(self.width, self.ports) self.trigger = trigger = Trigger(self.width, self.ports)
self.submodules.recorder = recorder = Recorder(self.width, self.depth) self.recorder = recorder = Recorder(self.width, self.depth)
self.comb += [ self.comb += [
sink.connect(trigger.sink), sink.connect(trigger.sink),
trigger.source.connect(recorder.trig_sink) trigger.source.connect(recorder.trig_sink)
] ]
if self.with_rle: if self.with_rle:
self.submodules.rle = rle = RunLengthEncoder(self.width) self.rle = rle = RunLengthEncoder(self.width)
self.comb += [ self.comb += [
sink.connect(rle.sink), sink.connect(rle.sink),
rle.source.connect(recorder.dat_sink) rle.source.connect(recorder.dat_sink)

4
miscope/trigger.py
View file

@ -124,9 +124,9 @@ class Trigger(Module, AutoCSR):
self.width = width self.width = width
self.ports = ports self.ports = ports
self.submodules.sum = Sum(len(ports)) self.sum = Sum(len(ports))
for i, port in enumerate(ports): for i, port in enumerate(ports):
setattr(self.submodules, "port"+str(i), port) setattr(self, "port"+str(i), port)
self.sink = Record(dat_layout(width)) self.sink = Record(dat_layout(width))
self.source = self.sum.source self.source = self.sum.source

10
miscope/uart2wishbone.py
View file

@ -14,8 +14,8 @@ class UART(Module, AutoCSR):
### ###
self.submodules.rx = UARTRX(pads, tuning_word) self.rx = UARTRX(pads, tuning_word)
self.submodules.tx = UARTTX(pads, tuning_word) self.tx = UARTTX(pads, tuning_word)
class Counter(Module): class Counter(Module):
def __init__(self, width): def __init__(self, width):
@ -75,12 +75,12 @@ class UART2Wishbone(Module, AutoCSR):
### ###
if share_uart: if share_uart:
self.submodules.uart_mux = UARTMux(pads) self.uart_mux = UARTMux(pads)
self.submodules.uart = UART(self.uart_mux.bridge_pads, clk_freq, baud) self.uart = UART(self.uart_mux.bridge_pads, clk_freq, baud)
self.shared_pads = self.uart_mux.shared_pads self.shared_pads = self.uart_mux.shared_pads
self.comb += self.uart_mux.sel.eq(self._sel.storage) self.comb += self.uart_mux.sel.eq(self._sel.storage)
else: else:
self.submodules.uart = UART(pads, clk_freq, baud) self.uart = UART(pads, clk_freq, baud)
uart = self.uart uart = self.uart

8
sim/tb_recorder_csr.py
View file

@ -81,10 +81,10 @@ class TB(Module):
self.csr_base = 0 self.csr_base = 0
# Recorder # Recorder
self.submodules.recorder = Recorder(32, 1024) self.recorder = Recorder(32, 1024)
# Csr # Csr
self.submodules.csrbankarray = csrgen.BankArray(self, self.csrbankarray = csrgen.BankArray(self,
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override]) lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
# Csr Master # Csr Master
@ -93,9 +93,9 @@ class TB(Module):
bus = Csr2Trans() bus = Csr2Trans()
regs = build_map(addrmap, bus.read_csr, bus.write_csr) regs = build_map(addrmap, bus.read_csr, bus.write_csr)
self.submodules.master = csr.Initiator(csr_transactions(bus, regs)) self.master = csr.Initiator(csr_transactions(bus, regs))
self.submodules.csrcon = csr.Interconnect(self.master.bus, self.csrbankarray.get_buses()) self.csrcon = csr.Interconnect(self.master.bus, self.csrbankarray.get_buses())
# Recorder Data # Recorder Data
def recorder_data(self, selfp): def recorder_data(self, selfp):

2
sim/tb_rle.py
View file

@ -26,7 +26,7 @@ class TB(Module):
def __init__(self): def __init__(self):
# Rle # Rle
self.submodules.rle = storage.RunLengthEncoder(16, 32) self.rle = storage.RunLengthEncoder(16, 32)
def do_simulation(self, selfp): def do_simulation(self, selfp):
selfp.rle._r_enable.storage = 1 selfp.rle._r_enable.storage = 1

8
sim/tb_trigger_csr.py
View file

@ -66,10 +66,10 @@ class TB(Module):
term1 = Term(32) term1 = Term(32)
term2 = Term(32) term2 = Term(32)
term3 = Term(32) term3 = Term(32)
self.submodules.trigger = Trigger(32, [term0, term1, term2, term3]) self.trigger = Trigger(32, [term0, term1, term2, term3])
# Csr # Csr
self.submodules.csrbankarray = csrgen.BankArray(self, self.csrbankarray = csrgen.BankArray(self,
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override]) lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
# Csr Master # Csr Master
@ -78,9 +78,9 @@ class TB(Module):
bus = Csr2Trans() bus = Csr2Trans()
regs = build_map(addrmap, bus.read_csr, bus.write_csr) regs = build_map(addrmap, bus.read_csr, bus.write_csr)
self.submodules.master = csr.Initiator(csr_transactions(bus, regs)) self.master = csr.Initiator(csr_transactions(bus, regs))
self.submodules.csrcon = csr.Interconnect(self.master.bus, self.csrbankarray.get_buses()) self.csrcon = csr.Interconnect(self.master.bus, self.csrbankarray.get_buses())
self.terms = [term0, term1, term2, term3] self.terms = [term0, term1, term2, term3]