soc/interconnect/wishbone: Make burst cycles support in SRAM optional

litex/soc/interconnect/axi.py

@@ -793,7 +793,7 @@ class AXILite2CSR(Module):
 # AXILite SRAM -------------------------------------------------------------------------------------
 
 class AXILiteSRAM(Module):
-    def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
+    def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=False):
         if bus is None:
             bus = AXILiteInterface()
         self.bus = bus

litex/soc/interconnect/wishbone.py

@@ -330,7 +330,7 @@ class Converter(Module):
 # Wishbone SRAM ------------------------------------------------------------------------------------
 
 class SRAM(Module):
-    def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=True):
+    def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=False):
         if bus is None:
             bus = Interface()
         self.bus = bus