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soc/interconnect/wishbone: Make burst cycles support in SRAM optional

This commit is contained in:
Rafal Kolucki 2022-03-24 13:42:45 +01:00
parent 8ef51a00ee
commit 54f897f446
2 changed files with 2 additions and 2 deletions
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2
litex/soc/interconnect/axi.py
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@ -793,7 +793,7 @@ class AXILite2CSR(Module):
# AXILite SRAM ------------------------------------------------------------------------------------- # AXILite SRAM -------------------------------------------------------------------------------------
class AXILiteSRAM(Module): class AXILiteSRAM(Module):
def __init__(self, mem_or_size, read_only=None, init=None, bus=None): def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=False):
if bus is None: if bus is None:
bus = AXILiteInterface() bus = AXILiteInterface()
self.bus = bus self.bus = bus

2
litex/soc/interconnect/wishbone.py
View File

@ -330,7 +330,7 @@ class Converter(Module):
# Wishbone SRAM ------------------------------------------------------------------------------------ # Wishbone SRAM ------------------------------------------------------------------------------------
class SRAM(Module): class SRAM(Module):
def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=True): def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=False):
if bus is None: if bus is None:
bus = Interface() bus = Interface()
self.bus = bus self.bus = bus