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soc/cores/cpu/rocket/core: align config (XCACHE, XTLB) to pythondata-cpu-rocket master

This commit is contained in:
Gwenhael Goavec-Merou 2024-03-07 09:00:32 +01:00
parent 149080fc8b
commit 54f8d90d38
1 changed files with 8 additions and 8 deletions
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16
litex/soc/cores/cpu/rocket/core.py
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@ -340,20 +340,20 @@ class Rocket(CPU):
soc.add_config("CPU_MMU", "sv39")
# Constants for Cache so we can add them in the DTS.
soc.add_config("CPU_DCACHE_SIZE", 4096) # CHECKME: correct/hardwired?
soc.add_config("CPU_DCACHE_WAYS", 2) # CHECKME: correct/hardwired?
soc.add_config("CPU_DCACHE_SIZE", 16384) # CHECKME: correct/hardwired?
soc.add_config("CPU_DCACHE_WAYS", 64) # CHECKME: correct/hardwired?
soc.add_config("CPU_DCACHE_BLOCK_SIZE", 64) # CHECKME: correct/hardwired?
soc.add_config("CPU_ICACHE_SIZE", 4096) # CHECKME: correct/hardwired?
soc.add_config("CPU_ICACHE_WAYS", 2) # CHECKME: correct/hardwired?
soc.add_config("CPU_ICACHE_SIZE", 16384) # CHECKME: correct/hardwired?
soc.add_config("CPU_ICACHE_WAYS", 64) # CHECKME: correct/hardwired?
soc.add_config("CPU_ICACHE_BLOCK_SIZE", 64) # CHECKME: correct/hardwired?
# Constants for TLB so we can add them in the DTS.
soc.add_config("CPU_DTLB_SIZE", 4) # CHECKME: correct/hardwired?
soc.add_config("CPU_DTLB_WAYS", 1) # CHECKME: correct/hardwired?
soc.add_config("CPU_DTLB_SIZE", 32) # CHECKME: correct/hardwired?
soc.add_config("CPU_DTLB_WAYS", 1) # CHECKME: correct/hardwired?
soc.add_config("CPU_ITLB_SIZE", 4) # CHECKME: correct/hardwired?
soc.add_config("CPU_ITLB_WAYS", 1) # CHECKME: correct/hardwired?
soc.add_config("CPU_ITLB_SIZE", 32) # CHECKME: correct/hardwired?
soc.add_config("CPU_ITLB_WAYS", 1) # CHECKME: correct/hardwired?
def do_finalize(self):
assert hasattr(self, "reset_address")