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soc/interconnect/axi: remove dead code (thanks gsomlo)

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This commit is contained in:
Florent Kermarrec 2019-03-27 21:15:14 +01:00
parent b682dacdd7
commit 552b0243b3
1 changed files with 0 additions and 2 deletions
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2
litex/soc/interconnect/axi.py
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@ -78,8 +78,6 @@ class AXI2Wishbone(Module):
NextState("DO-WRITE") NextState("DO-WRITE")
) )
) )
axi_ar_addr = Signal(32)
self.comb += axi_ar_addr.eq(axi.ar.addr - base_address)
fsm.act("DO-READ", fsm.act("DO-READ",
wishbone.stb.eq(1), wishbone.stb.eq(1),
wishbone.cyc.eq(1), wishbone.cyc.eq(1),