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cores/bitbang: Add TODO.

This commit is contained in:
Florent Kermarrec 2022-02-04 09:01:00 +01:00
parent 8dd2940bd0
commit 55a790308f
2 changed files with 3 additions and 1 deletions
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2
CHANGES
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@ -13,7 +13,7 @@
- openocd/stream: Simplify ECP5 JTAG-UART/JTAGBone use. - openocd/stream: Simplify ECP5 JTAG-UART/JTAGBone use.
- tools/litex_cli: Allow passing reg name to --read/--write. - tools/litex_cli: Allow passing reg name to --read/--write.
- soc/add_spi_sdcard: Allow optional Tristate (useful on ULX3S). - soc/add_spi_sdcard: Allow optional Tristate (useful on ULX3S).
- software/bios: Add new mem_cmd memory comparison commmand. - software/bios: Add new mem_cmd memory comparison command.
- cpu/rocket: Increase IRQ lines to 8. - cpu/rocket: Increase IRQ lines to 8.
- cpu/serv: Add MDU support. - cpu/serv: Add MDU support.
- cpu/marocchino: Add initial support. - cpu/marocchino: Add initial support.

2
litex/soc/cores/bitbang.py
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@ -85,6 +85,8 @@ class I2CMasterSim(I2CMaster):
# I2C Master Info Collection ---------------------------------------------------------------------- # I2C Master Info Collection ----------------------------------------------------------------------
# TODO: Find a more generic way to do it that would also apply to other peripherals?
def collect_i2c_info(soc): def collect_i2c_info(soc):
i2c_init = [] i2c_init = []
i2c_devs = [] i2c_devs = []