litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization

self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.

misoclib/mem/litesata/phy/k7/trx.py

@@ -575,7 +575,7 @@ class K7LiteSATAPHYTRX(Module):
 
                 # Receive Ports - CDR Ports
                     i_RXCDRFREQRESET=0,
-                    i_RXCDRHOLD=0,
+                    i_RXCDRHOLD=self.rxelecidle,
                     #o_RXCDRLOCK=,
                     i_RXCDROVRDEN=0,
                     i_RXCDRRESET=0,