Merge pull request #2146 from FlyGoat/bus-width
test: Include more bus option tests
This commit is contained in:
enjoy-digital
GitHub
commit
57333ee6c1
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Navaneeth Bhardwaj <navan93@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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import pexpect
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import sys
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import os
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class TestCPU(unittest.TestCase):
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def boot_test(self, cpu_type, jobs, cpu_variant="standard"):
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cmd = f'litex_sim --cpu-type={cpu_type} --cpu-variant={cpu_variant} --opt-level=O0 --jobs {jobs}'
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litex_prompt = [b'\033\[[0-9;]+mlitex\033\[[0-9;]+m>']
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is_success = True
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with open("/tmp/test_boot_log", "wb") as result_file:
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p = pexpect.spawn(cmd, timeout=None, logfile=result_file)
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try:
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match_id = p.expect(litex_prompt, timeout=1200)
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except pexpect.EOF:
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print('\n*** Premature termination')
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is_success = False
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except pexpect.TIMEOUT:
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print('\n*** Timeout ')
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is_success = False
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if not is_success:
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print(f'*** {cpu_type} Boot Failure')
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with open("/tmp/test_boot_log", "r") as result_file:
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print(result_file.read())
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else:
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p.terminate(force=True)
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print(f'*** {cpu_type} Boot Success')
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return is_success
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def test_cpu(self):
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tested_cpus = [
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#"cv32e40p", # (riscv / softcore)
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"femtorv", # (riscv / softcore)
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"firev", # (riscv / softcore)
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"marocchino", # (or1k / softcore)
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"naxriscv", # (riscv / softcore)
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"serv", # (riscv / softcore)
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"vexriscv", # (riscv / softcore)
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"vexriscv_smp", # (riscv / softcore)
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#"microwatt", # (ppc64 / softcore)
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"neorv32", # (riscv / softcore)
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]
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untested_cpus = [
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"blackparrot", # (riscv / softcore) -> Broken install?
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"cortex_m1", # (arm / softcore) -> Proprietary code.
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"cortex_m3", # (arm / softcore) -> Proprieraty code.
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"cv32e41p", # (riscv / softcore) -> Broken?
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"cva5", # (riscv / softcore) -> Needs to be tested.
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"cva6", # (riscv / softcore) -> Needs to be tested.
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"eos_s3", # (arm / hardcore) -> Hardcore.
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"gowin_emcu", # (arm / hardcore) -> Hardcore.
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"ibex", # (riscv / softcore) -> Broken since 2022.11.12.
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"lm32", # (lm32 / softcore) -> Requires LM32 toolchain.
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"minerva", # (riscv / softcore) -> Broken install? (Amaranth?)
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"mor1kx", # (or1k / softcore) -> Verilator compilation issue.
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"picorv32", # (riscv / softcore) -> Verilator compilation issue.
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"rocket", # (riscv / softcore) -> Not enough RAM in CI.
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"zynq7000", # (arm / hardcore) -> Hardcore.
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"zynqmp", # (aarch64 / hardcore) -> Hardcore.
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]
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jobs = os.cpu_count()
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for cpu in tested_cpus:
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with self.subTest(target=cpu):
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self.assertTrue(self.boot_test(cpu, jobs))
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@ -0,0 +1,128 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Navaneeth Bhardwaj <navan93@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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import pexpect
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import os
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import sys
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import tempfile
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import itertools
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class TestIntegration(unittest.TestCase):
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def boot_test(self, cpu_type="vexriscv", cpu_variant="standard", args=""):
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cmd = f'litex_sim --cpu-type={cpu_type} --cpu-variant={cpu_variant} {args} --opt-level=O0 --jobs {os.cpu_count()}'
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litex_prompt = [r'\033\[[0-9;]+mlitex\033\[[0-9;]+m>']
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is_success = True
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with tempfile.TemporaryFile(mode='w', prefix="litex_test") as log_file:
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log_file.writelines(f"Command: {cmd}")
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log_file.flush()
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p = pexpect.spawn(cmd, timeout=None, encoding=sys.getdefaultencoding(), logfile=log_file)
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try:
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match_id = p.expect(litex_prompt, timeout=1200)
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except pexpect.EOF:
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print('\n*** Premature termination')
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is_success = False
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except pexpect.TIMEOUT:
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print('\n*** Timeout ')
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is_success = False
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if not is_success:
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print(f'*** ({self.id()}) Boot Failure: {cmd}')
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log_file.seek(0)
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print(log_file.read())
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else:
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p.terminate(force=True)
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print(f'*** ({self.id()}) Boot Success: {cmd}')
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return is_success
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def test_cpu(self):
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tested_cpus = [
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#"cv32e40p", # (riscv / softcore)
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"femtorv", # (riscv / softcore)
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"firev", # (riscv / softcore)
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"marocchino", # (or1k / softcore)
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"naxriscv", # (riscv / softcore)
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"serv", # (riscv / softcore)
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"vexriscv", # (riscv / softcore)
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"vexriscv_smp", # (riscv / softcore)
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#"microwatt", # (ppc64 / softcore)
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"neorv32", # (riscv / softcore)
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]
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untested_cpus = [
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"blackparrot", # (riscv / softcore) -> Broken install?
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"cortex_m1", # (arm / softcore) -> Proprietary code.
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"cortex_m3", # (arm / softcore) -> Proprieraty code.
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"cv32e41p", # (riscv / softcore) -> Broken?
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"cva5", # (riscv / softcore) -> Needs to be tested.
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"cva6", # (riscv / softcore) -> Needs to be tested.
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"eos_s3", # (arm / hardcore) -> Hardcore.
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"gowin_emcu", # (arm / hardcore) -> Hardcore.
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"ibex", # (riscv / softcore) -> Broken since 2022.11.12.
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"lm32", # (lm32 / softcore) -> Requires LM32 toolchain.
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"minerva", # (riscv / softcore) -> Broken install? (Amaranth?)
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"mor1kx", # (or1k / softcore) -> Verilator compilation issue.
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"picorv32", # (riscv / softcore) -> Verilator compilation issue.
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"rocket", # (riscv / softcore) -> Not enough RAM in CI.
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"zynq7000", # (arm / hardcore) -> Hardcore.
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"zynqmp", # (aarch64 / hardcore) -> Hardcore.
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]
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for cpu in tested_cpus:
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with self.subTest(target=cpu):
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self.assertTrue(self.boot_test(cpu))
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def test_buses(self):
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options = [("--bus-standard", ["wishbone", "axi-lite", "axi"]),
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("--bus-data-width", [32, 64]),
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("--bus-address-width", [32, 64]),
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("--bus-interconnect", ["shared", "crossbar"])]
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# TODO: Investigate those failures
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blacklists = [
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# AXI-Lite with 64-bit data width and crossbar
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[
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("--bus-standard", ["axi-lite"]),
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("--bus-data-width", [64]),
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("--bus-interconnect", ["crossbar"])
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],
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# AXI with 64-bit data width
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[
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("--bus-standard", ["axi"]),
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("--bus-data-width", [64])
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]
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]
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def is_blacklisted(config):
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for blacklist in blacklists:
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matches = True
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for opt, values in blacklist:
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cfg_value = next(v for k,v in config if k == opt)
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if cfg_value not in values:
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matches = False
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break
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if matches:
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return True
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return False
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# Generate all combinations
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keys = [k for k,_ in options]
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values = [v for _,v in options]
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for combination in itertools.product(*values):
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config = list(zip(keys, combination))
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# Skip blacklisted combinations
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if is_blacklisted(config):
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continue
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# Build args string
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args = " ".join(f"{k}={v}" for k,v in config)
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with self.subTest(args=args):
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self.assertTrue(self.boot_test(args=args))
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