build/vhd2v_converter.py: fix params vs instance when conversion is disabled

2024-12-19 17:59:58 +01:00 · 2024-12-19 17:59:58 +01:00 · 8254a349f8
parent 6228d2b024
commit 8254a349f8
1 changed files with 4 additions and 1 deletions
--- a/litex/build/vhd2v_converter.py
+++ b/litex/build/vhd2v_converter.py
@ -138,7 +138,10 @@ class VHD2VConverter(Module):

        # platform able to synthesis verilog and vhdl -> no conversion
        if self._platform.support_mixed_language and not self._force_convert:
-            ip_params = self._params
+            if self._params:
+                ip_params = self._params
+            else:
+                ip_params = self._instance.items
            for file in self._sources:
                self._platform.add_source(file, library=self._work_package)
        else: # platform is only able to synthesis verilog -> convert vhdl to verilog