cores/cpu: Switch to automatic CPUs collection.
Simplify code/maintenance and will also enable out-of-tree CPUs support.
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2015-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2017-2018 Tim 'mithro' Ansell <me@mith.ro>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import inspect
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import importlib
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from migen import *
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# CPU ----------------------------------------------------------------------------------------------
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@ -30,14 +34,14 @@ class CPU(Module):
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pass
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class CPUNone(CPU):
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variants = ["standard"]
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data_width = 32
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endianness = "little"
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reset_address = 0x00000000
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io_regions = {0x00000000: 0x100000000} # origin, length
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periph_buses = []
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memory_buses = []
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mem_map = {
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variants = ["standard"]
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data_width = 32
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endianness = "little"
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reset_address = 0x00000000
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io_regions = {0x00000000: 0x100000000} # origin, length
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periph_buses = []
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memory_buses = []
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mem_map = {
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"csr" : 0x00000000,
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"ethmac" : 0x00020000, # FIXME: Remove.
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"spiflash" : 0x10000000, # FIXME: Remove.
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@ -70,76 +74,36 @@ CPU_GCC_TRIPLE_RISCV64 = (
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# CPUS ---------------------------------------------------------------------------------------------
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# LM32
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from litex.soc.cores.cpu.lm32 import LM32
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def collect_cpus():
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cpus = {
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# None.
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"None" : CPUNone,
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# External (CPU class provided externally by design/user)
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"external" : None,
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}
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path = os.path.dirname(__file__)
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# OpenRisc
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from litex.soc.cores.cpu.mor1kx import MOR1KX
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from litex.soc.cores.cpu.marocchino import Marocchino
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# Search for CPUs in cpu directory.
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for file in os.listdir(path):
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# OpenPower
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from litex.soc.cores.cpu.microwatt import Microwatt
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# Verify that it's a path...
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cpu_path = os.path.join(os.path.dirname(__file__), file)
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if not os.path.isdir(cpu_path):
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continue
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# RISC-V (32-bit)
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from litex.soc.cores.cpu.serv import SERV
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from litex.soc.cores.cpu.femtorv import FemtoRV
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from litex.soc.cores.cpu.picorv32 import PicoRV32
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from litex.soc.cores.cpu.minerva import Minerva
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from litex.soc.cores.cpu.vexriscv import VexRiscv
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from litex.soc.cores.cpu.vexriscv_smp import VexRiscvSMP
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from litex.soc.cores.cpu.ibex import Ibex
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from litex.soc.cores.cpu.cv32e40p import CV32E40P
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# ... and that core.py is present.
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cpu_core = os.path.join(cpu_path, "core.py")
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if not os.path.exists(cpu_core):
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continue
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# RISC-V (64-bit)
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from litex.soc.cores.cpu.rocket import RocketRV64
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from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
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# OK, it seems to be a CPU; now get the class and add it to dict.
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cpu = file
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cpu_module = f"litex.soc.cores.cpu.{cpu}.core"
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for cpu_name, cpu_cls in inspect.getmembers(importlib.import_module(cpu_module), inspect.isclass):
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if cpu.replace("_", "") == cpu_name.lower():
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cpus[cpu] = cpu_cls
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# Zynq
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from litex.soc.cores.cpu.zynq7000 import Zynq7000
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# Return collected CPUs.
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return cpus
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# EOS-S3
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from litex.soc.cores.cpu.eos_s3 import EOS_S3
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# Gowin EMCU
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from litex.soc.cores.cpu.gowin_emcu import GowinEMCU
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CPUS = {
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# None
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"None" : CPUNone,
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# External (CPU class provided externally by design/user)
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"external" : None,
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# LM32
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"lm32" : LM32,
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# OpenRisc
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"mor1kx" : MOR1KX,
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"marocchino" : Marocchino,
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# OpenPower
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"microwatt" : Microwatt,
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# RISC-V (32-bit)
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"serv" : SERV,
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"femtorv" : FemtoRV,
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"picorv32" : PicoRV32,
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"minerva" : Minerva,
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"vexriscv" : VexRiscv,
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"vexriscv_smp": VexRiscvSMP,
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"ibex" : Ibex,
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"cv32e40p" : CV32E40P,
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# RISC-V (64-bit)
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"rocket" : RocketRV64,
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"blackparrot" : BlackParrotRV64,
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# Zynq
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"zynq7000" : Zynq7000,
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# EOS-S3
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"eos_s3" : EOS_S3,
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# Gowin EMCU
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'gowin_emcu' : GowinEMCU
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}
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CPUS = collect_cpus()
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