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tools/litex_client: Use CSR base as base address on PCIe designs.

This commit is contained in:
Florent Kermarrec 2021-03-25 18:24:21 +01:00
parent 518aaeaacb
commit 58701cc48c
1 changed files with 8 additions and 0 deletions
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8
litex/tools/litex_client.py
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@ -90,6 +90,10 @@ def dump_identifier(port):
wb = RemoteClient(port=port) wb = RemoteClient(port=port)
wb.open() wb.open()
# On PCIe designs, CSR is remapped to 0 to limit BAR0 size.
if hasattr(wb.bases, "pcie_phy"):
wb.base_address = -wb.mems.csr.base
fpga_identifier = "" fpga_identifier = ""
for i in range(256): for i in range(256):
@ -106,6 +110,10 @@ def dump_registers(port):
wb = RemoteClient(port=port) wb = RemoteClient(port=port)
wb.open() wb.open()
# On PCIe designs, CSR is remapped to 0 to limit BAR0 size.
if hasattr(wb.bases, "pcie_phy"):
wb.base_address = -wb.mems.csr.base
for name, register in wb.regs.__dict__.items(): for name, register in wb.regs.__dict__.items():
print("0x{:08x} : 0x{:08x} {}".format(register.addr, register.read(), name)) print("0x{:08x} : 0x{:08x} {}".format(register.addr, register.read(), name))