sram: fix sub-word write
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@ -9,7 +9,7 @@ class SRAM:
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def get_fragment(self):
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# generate write enable signal
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we = Signal(BV(4))
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comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[3-i])
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comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[i])
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for i in range(4)]
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# split address
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nbits = bits_for(self.depth-1)
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