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litex
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Build your hardware, easily!
29 Commits 40 Branches 14 Tags 51 MiB
C 52.8%
Python 43.5%
Assembly 1.4%
SystemVerilog 1.3%
Makefile 0.3%
Other 0.6%
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Sebastien Bourdeauducq 58f4f78d2c sram: fix sub-word write 2012-02-06 23:13:35 +01:00
build Initial import 2011-12-13 17:33:12 +01:00
milkymist sram: fix sub-word write 2012-02-06 23:13:35 +01:00
software software: use new UART 2012-02-06 17:53:41 +01:00
tb/norflash Convert -> convert 2012-01-05 19:27:45 +01:00
tools Add tools 2012-02-05 19:14:24 +01:00
verilog uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
.gitignore Update gitignore 2012-02-05 20:01:14 +01:00
build.py Convert -> convert 2012-01-05 19:27:45 +01:00
constraints.py Multiply system clock 2011-12-17 15:00:18 +01:00
top.py sram: fix sub-word write 2012-02-06 23:13:35 +01:00