sram: fix sub-word write

This commit is contained in:
Sebastien Bourdeauducq 2012-02-06 23:13:35 +01:00
parent 5cde57cb65
commit 58f4f78d2c
2 changed files with 2 additions and 2 deletions

View File

@ -9,7 +9,7 @@ class SRAM:
def get_fragment(self):
# generate write enable signal
we = Signal(BV(4))
comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[3-i])
comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[i])
for i in range(4)]
# split address
nbits = bits_for(self.depth-1)

2
top.py
View File

@ -8,7 +8,7 @@ import constraints
def get():
MHz = 1000000
clk_freq = 80*MHz
sram_size = 4096 # in kilobytes
sram_size = 4096 # in bytes
clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
reset0 = m1reset.M1Reset()