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cores/hyperbus: Test and fix HyperRAM register read accesses. 

Seems OK:
Identification Register 0 : 00000e76
Identification Register 1 : 00000009
Configuration Register 0  : 00008f2f
Configuration Register 1  : 0000ffc1
reg_control: 302
reg_status:  2
reg_debug:   8
This commit is contained in:
Florent Kermarrec 2024-04-11 18:29:48 +02:00
parent 2384d6fbd4
commit 59756b4342
2 changed files with 50 additions and 2 deletions
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14
litex/soc/cores/hyperbus.py
View File

@ -52,6 +52,8 @@ class HyperRAM(LiteXModule):
self.reg_wdata = CSRStorage(16, description="Register Write Data.")
self.reg_rdata = CSRStatus( 16, description="Register Read Data.")
self.reg_debug = CSRStatus(32)
# # #
clk = Signal()
@ -148,6 +150,13 @@ class HyperRAM(LiteXModule):
self.reg_status.fields.read_done.eq(reg_read_done),
]
self.comb += [
self.reg_debug.status[0].eq(reg_write_req),
self.reg_debug.status[1].eq(reg_write_done),
self.reg_debug.status[2].eq(reg_read_req),
self.reg_debug.status[3].eq(reg_read_done),
]
# Command generation -----------------------------------------------------------------------
ashift = {8:1, 16:0}[dw]
self.comb += [
@ -159,7 +168,7 @@ class HyperRAM(LiteXModule):
0 : ca[0:40].eq(0x00_00_00_00_00), # Identification Register 0 (Read Only).
1 : ca[0:40].eq(0x00_00_00_00_01), # Identification Register 1 (Read Only).
2 : ca[0:40].eq(0x00_01_00_00_00), # Configuration Register 0.
3 : ca[0:40].eq(0x00_01_00_00_00), # Configuration Register 1.
3 : ca[0:40].eq(0x00_01_00_00_01), # Configuration Register 1.
}),
).Else(
ca[47].eq(~bus.we), # R/W#
@ -263,6 +272,7 @@ class HyperRAM(LiteXModule):
burst_timer.wait.eq(1),
# Set CSn.
cs.eq(1),
ca_active.eq(reg_read_req),
# Send Data on DQ/RWDS (for write).
If(bus_we,
dq.oe.eq(1),
@ -290,7 +300,7 @@ class HyperRAM(LiteXModule):
# Read Ack (when dat_r ready).
If((n == 0) & ~first,
If(reg_read_req,
reg_buffer.source.valid.eq(1),
reg_buffer.source.ready.eq(1),
NextValue(reg_read_done, 1),
NextValue(self.reg_rdata.status, bus.dat_r),
NextState("IDLE"),

38
litex/soc/software/bios/main.c
View File

@ -175,6 +175,44 @@ __attribute__((__used__)) int main(int i, char **c)
sdr_ok = 1;
/* HyperRAM Register access test */
hyperram_reg_control_write(
0 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
1 << CSR_HYPERRAM_REG_CONTROL_READ_OFFSET |
0 << CSR_HYPERRAM_REG_CONTROL_REG_OFFSET
);
while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
printf("Identification Register 0 : %08lx\n", hyperram_reg_rdata_read());
hyperram_reg_control_write(
0 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
1 << CSR_HYPERRAM_REG_CONTROL_READ_OFFSET |
1 << CSR_HYPERRAM_REG_CONTROL_REG_OFFSET
);
while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
printf("Identification Register 1 : %08lx\n", hyperram_reg_rdata_read());
hyperram_reg_control_write(
0 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
1 << CSR_HYPERRAM_REG_CONTROL_READ_OFFSET |
2 << CSR_HYPERRAM_REG_CONTROL_REG_OFFSET
);
while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
printf("Configuration Register 0 : %08lx\n", hyperram_reg_rdata_read());
hyperram_reg_control_write(
0 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
1 << CSR_HYPERRAM_REG_CONTROL_READ_OFFSET |
3 << CSR_HYPERRAM_REG_CONTROL_REG_OFFSET
);
while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
printf("Configuration Register 1 : %08lx\n", hyperram_reg_rdata_read());
printf("reg_control: %x\n", hyperram_reg_control_read());
printf("reg_status: %x\n", hyperram_reg_status_read());
printf("reg_debug: %x\n", hyperram_reg_debug_read());
#if defined(CSR_ETHMAC_BASE) || defined(MAIN_RAM_BASE) || defined(CSR_SPIFLASH_CORE_BASE)
printf("--========== \e[1mInitialization\e[0m ============--\n");
#ifdef CSR_ETHMAC_BASE