cores/hyperbus: Test and fix HyperRAM register read accesses.
Seems OK: Identification Register 0 : 00000e76 Identification Register 1 : 00000009 Configuration Register 0 : 00008f2f Configuration Register 1 : 0000ffc1 reg_control: 302 reg_status: 2 reg_debug: 8
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@ -52,6 +52,8 @@ class HyperRAM(LiteXModule):
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self.reg_wdata = CSRStorage(16, description="Register Write Data.")
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self.reg_wdata = CSRStorage(16, description="Register Write Data.")
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self.reg_rdata = CSRStatus( 16, description="Register Read Data.")
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self.reg_rdata = CSRStatus( 16, description="Register Read Data.")
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self.reg_debug = CSRStatus(32)
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# # #
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# # #
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clk = Signal()
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clk = Signal()
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@ -148,6 +150,13 @@ class HyperRAM(LiteXModule):
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self.reg_status.fields.read_done.eq(reg_read_done),
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self.reg_status.fields.read_done.eq(reg_read_done),
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]
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]
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self.comb += [
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self.reg_debug.status[0].eq(reg_write_req),
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self.reg_debug.status[1].eq(reg_write_done),
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self.reg_debug.status[2].eq(reg_read_req),
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self.reg_debug.status[3].eq(reg_read_done),
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]
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# Command generation -----------------------------------------------------------------------
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# Command generation -----------------------------------------------------------------------
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ashift = {8:1, 16:0}[dw]
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ashift = {8:1, 16:0}[dw]
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self.comb += [
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self.comb += [
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@ -159,7 +168,7 @@ class HyperRAM(LiteXModule):
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0 : ca[0:40].eq(0x00_00_00_00_00), # Identification Register 0 (Read Only).
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0 : ca[0:40].eq(0x00_00_00_00_00), # Identification Register 0 (Read Only).
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1 : ca[0:40].eq(0x00_00_00_00_01), # Identification Register 1 (Read Only).
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1 : ca[0:40].eq(0x00_00_00_00_01), # Identification Register 1 (Read Only).
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2 : ca[0:40].eq(0x00_01_00_00_00), # Configuration Register 0.
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2 : ca[0:40].eq(0x00_01_00_00_00), # Configuration Register 0.
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3 : ca[0:40].eq(0x00_01_00_00_00), # Configuration Register 1.
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3 : ca[0:40].eq(0x00_01_00_00_01), # Configuration Register 1.
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}),
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}),
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).Else(
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).Else(
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ca[47].eq(~bus.we), # R/W#
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ca[47].eq(~bus.we), # R/W#
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@ -263,6 +272,7 @@ class HyperRAM(LiteXModule):
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burst_timer.wait.eq(1),
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burst_timer.wait.eq(1),
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# Set CSn.
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# Set CSn.
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cs.eq(1),
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cs.eq(1),
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ca_active.eq(reg_read_req),
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# Send Data on DQ/RWDS (for write).
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# Send Data on DQ/RWDS (for write).
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If(bus_we,
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If(bus_we,
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dq.oe.eq(1),
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dq.oe.eq(1),
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@ -290,7 +300,7 @@ class HyperRAM(LiteXModule):
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# Read Ack (when dat_r ready).
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# Read Ack (when dat_r ready).
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If((n == 0) & ~first,
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If((n == 0) & ~first,
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If(reg_read_req,
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If(reg_read_req,
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reg_buffer.source.valid.eq(1),
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reg_buffer.source.ready.eq(1),
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NextValue(reg_read_done, 1),
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NextValue(reg_read_done, 1),
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NextValue(self.reg_rdata.status, bus.dat_r),
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NextValue(self.reg_rdata.status, bus.dat_r),
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NextState("IDLE"),
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NextState("IDLE"),
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@ -175,6 +175,44 @@ __attribute__((__used__)) int main(int i, char **c)
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sdr_ok = 1;
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sdr_ok = 1;
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/* HyperRAM Register access test */
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hyperram_reg_control_write(
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0 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
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1 << CSR_HYPERRAM_REG_CONTROL_READ_OFFSET |
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0 << CSR_HYPERRAM_REG_CONTROL_REG_OFFSET
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);
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while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
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printf("Identification Register 0 : %08lx\n", hyperram_reg_rdata_read());
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hyperram_reg_control_write(
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0 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
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1 << CSR_HYPERRAM_REG_CONTROL_READ_OFFSET |
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1 << CSR_HYPERRAM_REG_CONTROL_REG_OFFSET
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);
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while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
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printf("Identification Register 1 : %08lx\n", hyperram_reg_rdata_read());
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hyperram_reg_control_write(
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0 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
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1 << CSR_HYPERRAM_REG_CONTROL_READ_OFFSET |
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2 << CSR_HYPERRAM_REG_CONTROL_REG_OFFSET
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);
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while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
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printf("Configuration Register 0 : %08lx\n", hyperram_reg_rdata_read());
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hyperram_reg_control_write(
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0 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
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1 << CSR_HYPERRAM_REG_CONTROL_READ_OFFSET |
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3 << CSR_HYPERRAM_REG_CONTROL_REG_OFFSET
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);
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while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
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printf("Configuration Register 1 : %08lx\n", hyperram_reg_rdata_read());
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printf("reg_control: %x\n", hyperram_reg_control_read());
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printf("reg_status: %x\n", hyperram_reg_status_read());
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printf("reg_debug: %x\n", hyperram_reg_debug_read());
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#if defined(CSR_ETHMAC_BASE) || defined(MAIN_RAM_BASE) || defined(CSR_SPIFLASH_CORE_BASE)
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#if defined(CSR_ETHMAC_BASE) || defined(MAIN_RAM_BASE) || defined(CSR_SPIFLASH_CORE_BASE)
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printf("--========== \e[1mInitialization\e[0m ============--\n");
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printf("--========== \e[1mInitialization\e[0m ============--\n");
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#ifdef CSR_ETHMAC_BASE
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#ifdef CSR_ETHMAC_BASE
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