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Fix off-by-one error on almost full condition for prefetch 

This causes a DRC error on the Xilinx tools when the prefetch
lines setting is 1. Don't know why this wasn't caught earlier,
but it just popped up in CI.
This commit is contained in:
bunnie 2020-03-24 14:11:23 +08:00 committed by Florent Kermarrec
parent d62ef38c4b
commit 5a402264d0
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/spi_opi.py
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@ -494,7 +494,7 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc):
p_DATA_WIDTH = 32, p_DATA_WIDTH = 32,
p_FIRST_WORD_FALL_THROUGH = "TRUE", p_FIRST_WORD_FALL_THROUGH = "TRUE",
p_ALMOST_EMPTY_OFFSET = 6, p_ALMOST_EMPTY_OFFSET = 6,
p_ALMOST_FULL_OFFSET = (512- (8*prefetch_lines)), p_ALMOST_FULL_OFFSET = (511 - (8*prefetch_lines)),
o_ALMOSTEMPTY = rx_almostempty, o_ALMOSTEMPTY = rx_almostempty,
o_ALMOSTFULL = rx_almostfull, o_ALMOSTFULL = rx_almostfull,