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soc/add_etherbone: Fix UDPIPCore clock domain (should still run at eth_clk even if Etherbone is running in sys_clk) since data-width convertion is done on UDP.

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This commit is contained in:
Florent Kermarrec 2021-03-08 13:46:56 +01:00
parent a1e54671be
commit 5af8e5c934
1 changed files with 2 additions and 1 deletions
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litex/soc/integration/soc.py
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@ -1408,7 +1408,8 @@ class LiteXSoC(SoC):
clk_freq = self.clk_freq)
ethcore = ClockDomainsRenamer({
"eth_tx": phy_cd + "_tx",
"eth_rx": phy_cd + "_rx"})(ethcore)
"eth_rx": phy_cd + "_rx",
"sys": phy_cd + "_rx"})(ethcore)
self.submodules.ethcore = ethcore
# Clock domain renaming