Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/add_etherbone: Fix UDPIPCore clock domain (should still run at eth_clk even if Etherbone is running in sys_clk) since data-width convertion is done on UDP.

This commit is contained in:
Florent Kermarrec 2021-03-08 13:46:56 +01:00
parent a1e54671be
commit 5af8e5c934
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
litex/soc/integration/soc.py
View File

@ -1408,7 +1408,8 @@ class LiteXSoC(SoC):
clk_freq = self.clk_freq) clk_freq = self.clk_freq)
ethcore = ClockDomainsRenamer({ ethcore = ClockDomainsRenamer({
"eth_tx": phy_cd + "_tx", "eth_tx": phy_cd + "_tx",
"eth_rx": phy_cd + "_rx"})(ethcore) "eth_rx": phy_cd + "_rx",
"sys": phy_cd + "_rx"})(ethcore)
self.submodules.ethcore = ethcore self.submodules.ethcore = ethcore
# Clock domain renaming # Clock domain renaming