interconnect/ahb/AHB2Wishbone: Fix size check that is too restrictive, can be <= log2_int(ahb.data_width//8).

2024-01-04 13:09:31 +01:00 · 2024-01-04 13:09:31 +01:00 · 5bbcda4d5c
parent 6a6837062a
commit 5bbcda4d5c
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/interconnect/ahb.py
+++ b/litex/soc/interconnect/ahb.py
@ -70,7 +70,7 @@ class AHB2Wishbone(LiteXModule):
        fsm.act("IDLE",
            ahb.readyout.eq(1),
            If(ahb.sel &
-              (ahb.size  == wishbone_adr_shift) &
+              (ahb.size  <= log2_int(ahb.data_width//8)) &
              (ahb.trans == TransferType.NONSEQUENTIAL),
               NextValue(wishbone.adr,   ahb.addr[wishbone_adr_shift:]),
               NextValue(wishbone.dat_w, ahb.wdata),