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cores/dma: add stream.last support on WishboneDMAReader.

This commit is contained in:
Florent Kermarrec 2020-07-09 12:18:09 +02:00
parent 146ead4c4c
commit 5c332e4b58
1 changed files with 4 additions and 2 deletions
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6
litex/soc/cores/dma.py
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@ -39,7 +39,7 @@ class WishboneDMAReader(Module, AutoCSR):
def __init__(self, bus, endianness="little", with_csr=False): def __init__(self, bus, endianness="little", with_csr=False):
assert isinstance(bus, wishbone.Interface) assert isinstance(bus, wishbone.Interface)
self.bus = bus self.bus = bus
self.sink = sink = stream.Endpoint([("address", bus.adr_width)]) self.sink = sink = stream.Endpoint([("address", bus.adr_width, ("last", 1))])
self.source = source = stream.Endpoint([("data", bus.data_width)]) self.source = source = stream.Endpoint([("data", bus.data_width)])
# # # # # #
@ -60,6 +60,7 @@ class WishboneDMAReader(Module, AutoCSR):
) )
fsm.act("SOURCE-WRITE", fsm.act("SOURCE-WRITE",
source.valid.eq(1), source.valid.eq(1),
source.last.eq(sink.last),
source.data.eq(data), source.data.eq(data),
If(source.ready, If(source.ready,
sink.ready.eq(1), sink.ready.eq(1),
@ -99,10 +100,11 @@ class WishboneDMAReader(Module, AutoCSR):
) )
fsm.act("RUN", fsm.act("RUN",
self.sink.valid.eq(1), self.sink.valid.eq(1),
self.sink.last.eq(offset == (length - 1)),
self.sink.address.eq(base + offset), self.sink.address.eq(base + offset),
If(self.sink.ready, If(self.sink.ready,
NextValue(offset, offset + 1), NextValue(offset, offset + 1),
If(offset == (length - 1), If(self.sink.last,
If(self._loop.storage, If(self._loop.storage,
NextValue(offset, 0) NextValue(offset, 0)
).Else( ).Else(