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Merge pull request #44 from felixheld/nexys_video-dram-fix 

Fix DDR3 on nexys_video
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Tim Ansell 2018-01-12 14:08:03 +11:00 committed by GitHub
parent c2c622691c 4a3454107a
commit 5c95c8ead0
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1 changed files with 2 additions and 2 deletions
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4
litex/boards/targets/nexys_video.py
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@ -97,8 +97,8 @@ class BaseSoC(SoCSDRAM):
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 3)
self.add_constant("A7DDRPHY_DELAY", 14)
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,