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cores/spi_mmap: fix data if bus width > length 

Details:
* 32bit bus write to 8 and 16bit MSB first slot resulted
  in shifted data on mosi.
* 32bit read from 8 and 16bit LSB first slot resulted
  with shifted data in fifo.
Fixes 2 tests - all current tests now pass.
This commit is contained in:
Andrew Dennison 2024-02-25 11:15:38 +11:00
parent 422b02cc16
commit 5d1fa7b6ca
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/spi/spi_mmap.py
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@ -591,7 +591,7 @@ class SPIEngine(LiteXModule):
# MSB First. # MSB First.
If(spi_bitorder == SPI_SLOT_BITORDER_MSB_FIRST, If(spi_bitorder == SPI_SLOT_BITORDER_MSB_FIRST,
# TX copy/bitshift. # TX copy/bitshift.
Case(spi_length, { Case(spi.length, {
8 : spi.mosi[24:32].eq(sink.data[0: 8]), 8 : spi.mosi[24:32].eq(sink.data[0: 8]),
16 : spi.mosi[16:32].eq(sink.data[0:16]), 16 : spi.mosi[16:32].eq(sink.data[0:16]),
32 : spi.mosi[ 0:32].eq(sink.data[0:32]), 32 : spi.mosi[ 0:32].eq(sink.data[0:32]),
@ -604,7 +604,7 @@ class SPIEngine(LiteXModule):
# TX copy. # TX copy.
spi.mosi.eq(sink.data[::-1]), spi.mosi.eq(sink.data[::-1]),
# RX copy/bitshift. # RX copy/bitshift.
Case(spi_length, { Case(spi.length, {
8 : source.data[0: 8].eq(spi.miso[::-1][24:32]), 8 : source.data[0: 8].eq(spi.miso[::-1][24:32]),
16 : source.data[0:16].eq(spi.miso[::-1][16:32]), 16 : source.data[0:16].eq(spi.miso[::-1][16:32]),
32 : source.data[0:32].eq(spi.miso[::-1][ 0:32]), 32 : source.data[0:32].eq(spi.miso[::-1][ 0:32]),